Configuration Of Adc Modules - STMicroelectronics SPC572L series Reference Manual

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Analog-to-digital converter (ADC) configuration
SAR ADCB, most analog input pins are routed to either the Sigma-Delta or SAR ADCs, but
never both.
and 80-pin packages.
ADC
instance
Analog input pins
AN[0:7]
AN[16:17]
SAR ADCB
AN[36:39]
AN[58:61]
SAR ADC0 AN[0:7]
SAR ADC4 AN[58:61]
AN[36:37]
SD ADC3
AN[38:39]
1. For the Sigma-Delta mux inputs AN[x], the positive and negative input terminals are selected in the Sigma-Delta ADC
digital interface.
34.2

Configuration of ADC modules

The following sections describe device-specific details for the following modules:
Section 34.2.1, Sigma-Delta Analog-to-Digital Converter (SDADC)
Section 34.2.2, Successive Approximation Register Analog-to-Digital Converter
(SARADC)
34.2.1
Sigma-Delta Analog-to-Digital Converter (SDADC)
There is one independent Sigma-Delta ADC on SPC572Lx. Refer to
subsystem block diagram.
The following sections describe configuration details:
Section 34.2.1.1, Sigma-Delta ADC external signal description
Section 34.2.1.2, Sigma-Delta ADC integration diagram
Section 34.2.1.3, Sigma-Delta ADC analog input multiplexing
Section 34.2.1.4, Sigma-Delta ADC clock sources
Section 34.2.1.5, Sigma-Delta ADC starting/triggering
Section 34.2.1.6, Sigma-Delta ADC external modulator
Section 34.2.1.7, Conversion result interrupt/DMA gating signal
Section 34.2.1.8, Sigma-Delta ADC analog input channel selection
For detailed module information, refer to the Sigma-Delta Analog-to-Digital Converter
(SDADC) Digital Interface chapter.
694/2058
Table 339
gives the analog input pin assignment for both SPC572Lx 100-pin
Table 339. SPC572Lx analog input pin multiplexing
80-pin QFP
Mux input
AN[0:7]
AN[16:17]
AN[36:39]
AN[58:61]
AN[0:7]
AN[58:61]
AN[0:1]
AN[2:3]
DocID027809 Rev 4
(1)
Analog input pins
AN[0:8]
AN[16:17]
AN[24]
AN[36:39]
AN[52:53]
AN[56:61]
AN[0:8]
AN[52:53]
AN[56:61]
AN[36:37]
AN[38:39]
RM0400
100-pin QFP
Mux input
AN[0:8]
AN[16:17]
AN[24]
AN[36:39]
AN[52:53]
AN[56:61]
AN[0:8]
AN[52:53]
AN[56:61]
AN[0:1]
AN[2:3]
Figure 303
for the ADC
1

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