Full Duplex Flow Control - STMicroelectronics SPC572L series Reference Manual

RM0400
48.5.13

Full duplex flow control

Full-duplex flow control allows you to transmit pause frames and to detect received pause
frames. Upon detection of a pause frame, MAC data frame transmission stops for a given
pause duration.
To enable PAUSE frame detection, the FEC must operate in full-duplex mode (TCR[FDEN]
set) with flow control (RCR[FCE] set). The FEC detects a pause frame when the fields of the
incoming frame match the pause frame specifications, as shown in
the receive status associated with the frame should indicate that the frame is valid.
48-bit destination address
The receiver and microcontroller modules perform PAUSE frame detection. The
microcontroller runs an address recognition subroutine to detect the specified pause frame
destination address, while the receiver detects the type and opcode pause frame fields. On
detection of a pause frame, TCR[GTS] is set by the FEC internally. When transmission has
paused, the EIR[GRA] interrupt is asserted and the pause timer begins to increment. The
pause timer uses the transmit backoff timer hardware for tracking the appropriate collision
backoff time in half-duplex mode. The pause timer increments once every slot time, until
OPD[PAUSE_DUR] slot times have expired. On OPD[PAUSE_DUR] expiration, TCR[GTS]
is cleared allowing MAC data frame transmission to resume. The receive flow control pause
status bit (TCR[RFC_PAUSE]) is set while the transmitter pauses due to reception of a
pause frame.
To transmit a pause frame, the FEC must operate in full-duplex mode and you must set flow
control pause (TCR[TFC_PAUSE]). After TCR[TFC_PAUSE] is set, the transmitter sets
TCR[GTS] internally. When the transmission of data frames stops, the EIR[GRA] (graceful
stop complete) interrupt asserts and the pause frame is transmitted.
TCR[TFC_PAUSE,GTS] are then cleared internally.
You must specify the desired pause duration in the OPD register.
When the transmitter pauses due to receiver/microcontroller pause frame detection,
TCR[TFC_PAUSE] may remain set and cause the transmission of a single pause frame. In
this case, the EIR[GRA] interrupt is not asserted.
Table 787. Destination address to 6-bit hash(Continued)
48-bit DA
9DFF_FFFF_FFFF
BDFF_FFFF_FFFF
Table 788. PAUSE frame field specification
48-bit source address
16-bit type
16-bit opcode
16-bit PAUSE duration
DocID027809 Rev 4
Fast Ethernet Controller (FEC)
6-bit hash
(in hex)
3Eh
3Fh
0180_C200_0001h or Physical Address
Any
8808h
0001h
0000h – FFFFh
Hash decimal value
62
63
Table 788. In addition,
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