Single Read Access - STMicroelectronics SPC572L series Reference Manual

RM0400
66.17.3

Single read access

1. Initialize the Read/Write Access Address Register (RWA) through the access method
outlined in
follows:
a)
2. Initialize the Read/Write Access Control/Status Register (RWCS) through the access
method outlined in
the bits as follows:
a)
b)
c)
d)
e)
f)
Note: Access Count (CNT) of 14'h0000 or 14'h0001 will perform a single access.
3. The Nexus block will then arbitrate for the AHB system bus and the read data will be
transferred from the AHB to the RWD Register. The nex_ahb_start output will be asserted
during the first clock of the address phase of the transfer. When the access has completed
without error, Nexus clears the ERR bit and sets the DV bit in the RWCS Register and
asserts the nex_rdy_b pin (see
access has completed with an error, the nex_err_b pin will be asserted, the ERR bit
will be set and the DV bit will be cleared to indicate an error has occurred, and the
nex_rdy_b pin will not be asserted. Once ERR or DV has been set, this indicates that
the device is ready for the next access, or that an error has occurred. The AC bit will be
cleared in either case.
4. The data can then be read from the Read/Write Access Data Register (RWD) through
the access method outlined in
Note: Only the nex_ahb_start, nex_rdy_b, and nex_err_b pins as well as the AC, DV and ERR
bits within the RWCS provide Read/Write Access status to the external development tool.
66.17.4 Block read access
1. For a block read access, follow Steps 1 and 2 outlined in
access
CNT field in the RWCS Register.
2. The Nexus block will then arbitrate for the AHB system bus and the read data will be
transferred from the AHB to the RWD Register. When the access has completed
without error, Nexus clears the ERR bit and sets the DV bit in the RWCS Register and
asserts the nex_rdy_b pin (see
access has completed with an error, the nex_err_b pin will be asserted, the ERR bit
will be set and the DV bit will be cleared to indicate an error has occurred, and the
nex_rdy_b pin will not be asserted. Once ERR or DV has been set, this indicates that
the device is ready for the next access, or that an error has occurred. The AC bit will be
cleared in either case.
3. When the transfer has completed without error, the address from the RWA Register is
incremented to the next word size (specified in the SZ field), the number from the CNT
field is decremented, Nexus clears the ERR bit and sets the DV bit in the RWCS
Register, and asserts the nex_rdy_b pin (see
Section 66.5, Nexus 3 Register Access via
Read Address 32h'xxxxxxxx (read address)
→
Section 66.5, Nexus 3 Register Access via
Access Control (AC)
→
Map Select (MAP)
→
Access Priority (PR)
→
Read/Write (RW) 1b'0 (read access)
→
Word Size (SZ) → 3b'0xx (32-bit, 16-bit, 8-bit)
Access Count (CNT)
→
to initialize the registers, but using a value greater than one (14'h0001) for the
DocID027809 Rev 4
1b'1 (to indicate start access)
3b'000 (primary memory map)
2b'11 (highest priority)
14h'0000 or 14h'0001(single access)
Table 1110 for detail on nex_rdy_b). Otherwise, if the
Section 66.5, Nexus 3 Register Access via
Table 1110 for detail on nex_rdy_b). Otherwise, if the
Table 1110
e200z215An3 Nexus 3 Module
JTAG/OnCE. Configure as
JTAG/OnCE. Configure
JTAG/OnCE.
Section 66.17.3, Single read
for detail on nex_rdy_b).
1971/2058
1982