Figure 587. Dspi Clock And Transfer Attributes Register (In Slave Mode) (Dspi_Ctarn_Slave) - STMicroelectronics SPC572L series Reference Manual

Deserial Serial Peripheral Interface (DSPI)
46.3.4 DSPI Clock and Transfer Attributes Register (In Slave Mode)
(DSPI_CTARn_SLAVE)
When the DSPI is configured as:
•
SPI master – the CTAS field in the command portion of the TX FIFO entry selects
which CTAR is used.
•
SPI bus slave – the CTAR0 register is used.
•
DSI master – the DSICTAS field in the DSPI DSI Configuration Register 0 (DSICR0)
selects which CTAR is used.
•
DSI bus slave – the CTAR1 register is used.
In CSI Configuration, the transfer attributes are based on whether the current frame is:
•
SPI data – follow the protocol described for SPI Configuration,
•
DSI data – follow the protocol described for DSI Configuration.
CSI Configuration is valid only in master mode.
TSB mode sets some limitations on transfer attributes:
•
Clock phase is forced to be CPHA = 1 and the CPHA bit setting has no effect.
•
PCS lines are driven at the driving edge of the SCK clock together with SOUT, so PCS
assertion and negation delays control is unavailable and PCSSCK, PASC, CSSCK and
ASC fields have no effect.
•
Delay after transfer can be set from 1 to 64 serial clocks via PDT and DT fields.
Address: Base + 0x000C
0 1
R
FMSZ
W
Reset 0 1
16 17
R 0 0
W
Reset 0 0

Figure 587. DSPI Clock and Transfer Attributes Register (In Slave Mode) (DSPI_CTARn_SLAVE)

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Table 615. DSPI baud rate scaler(Continued)
CTARn[BR]
1001
1010
1011
1100
1101
1110
1111
2 3 4 5
1 1 1 0
18 19 20 21
0 0 0 0
0 0 0 0
DocID027809 Rev 4
Baud rate scaler value
6 7 8 9
PE PP
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
512
1024
2048
4096
8192
16384
32768
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
0 0 0 0
RM0400
14 15
0 0
0 0
30 31
0 0
0 0