Array Integrity Considerations - STMicroelectronics SPC572L series Reference Manual

Flash memory controller (PFLASH Controller)
In the event of a non-correctable error detection, a fixed, illegal opcode value is returned to
the requesting master as determined by the requesting address, and the non-correctable
error event is suppressed from being reported.
28.5.13.2 Flash address generation check
Functional safety coverage of the address and data are handled by ECC performed within
the flash and e2eECC performed at the master. Functional safety coverage of the address
path and control within the flash memory controller rely on a feedback path between the
flash controller and flash. Recall on a requested access to flash, the flash memory controller
must decode the system AHB bus signals to generate the corresponding flash interface
signals to invoke a flash lookup. In addition to providing the requested read data, the flash
also provides output sidebands reflecting the encoded address and block selects used to
perform the actual row lookup:
fl_enc_addr[23:2]
fl_enc_error
This sideband information is used by the flash memory controller to verify the expected
transaction. If a mismatch is detected, indicating a failure in the address generation or
control logic within the flash memory controller or the transmission path between the flash
memory controller and flash array, the event is forwarded to the Fault Collection and Control
Unit (FCCU) and the corresponding buffer is invalidated. The flash memory controller has a
separate MEMU reporting interface associated with each AHB port: p0 and p1.
28.5.13.3 On-Chip Overlay RAM Feedback Check
The integrity of the address and data on an overlay RAM transaction is covered by e2eECC
check performed by the requesting master. Functional safety coverage of the address path
and control within theflash memory controller is handled by a transaction monitor which
verifies the integrity of the transactions between theflash memory controller and the on-chip
overlay RAM arrays.The function of the transaction monitor relies on a feedback path
between theflash memory controller and the on-chip overlay RAM arrays, wherein the RAM
provides latched address and control feedback outputs as an indication of received inputs
when a RAM access is initiated. This feedback information is used by theflash memory
controller transaction monitor to verify the expected transaction.
28.5.14

Array integrity considerations

During an array integrity sequence, the flash array ignores any incoming read requests. The
flash provides an output sideband, fl_aid, which indicates when an array integrity sequence
is in progress. When fl_aid is asserted, the flash memory controller aborts any incoming
flash access requests and terminates the system bus transfer with an error.
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