Table 580. Calibration Configuration Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

CAN Subsystem

Table 580. Calibration Configuration Register field descriptions

Field
Software Reset
Writing a '1' to this bit will reset the calibration FSM to state Not_Calibrated (CSTAT.CALS = "00").
0
The Calibration Watchdog value CWD.WDV is also reset. Registers CCFG, CSTAT and the
SWR
Calibration Watchdog configuration CWD.WDC are unchanged. The bit remains set until reset has
completed.
1:11 Reserved
Clock Divider
The clock divider has to be configured when the clock calibration is bypassed (BCC = '1') to assure
that the M_CAN requirement m_can_cclk . m_can_hclk is fulfilled.
0000 Divide by 1
0001 Divide by 2
0010 Divide by 4
0011 Divide by 6
0100 Divide by 8
0101 Divide by 10
12:15
0110 Divide by 12
CDIV
0111 Divide by 14
1000 Divide by 16
1001 Divide by 18
1010 Divide by 20
1011 Divide by 22
1100 Divide by 24
1101 Divide by 26
1110 Divide by 28
1111 Divide by 30
Oscillator Clock Periods Minimum
Configures the minimum number of cu_pclk periods in two CAN bit times. OCPM is used in Basic
Calibration to avoid false measurements in case of glitches on the bus line. The configured number
16:23
of cu_pclk periods is OCPM • 32. The configuration depends on the cu_pclk frequency (80 MHz to
OCPM
500 MHz) and the bit rate configured in the attached M_CANs (125 kbit/s to 1 Mbit/s). It is
recommended to configure a value slightly below two CAN bit times. The reset value is 1.6 bit
times at 80 MHz cu_pclk and 1 Mbit/s CAN bit rate.
Calibration Field Length
24
0 Calibration field length is 32 bits
CFL
1 Calibration field length is 64 bits
Bypass Clock Calibration
If this bit is set, the clock input cu_pclk is routed to the time quanta clock output cu_tqc through a
clock divider configurable via CDIV, cu_cok is always '1'. In this case the baud rate prescaler of the
25
connected M_CANs has to be configured to generate the M_CAN internal time quanta clock.
BCC
0 Clock calibration unit generates time quanta clock cu_tqc
1 Clock calibration unit bypassed
Note: As long as cu_pclk is equal or above 80 MHz the Clock Calibration on CAN unit is functional,
even when BCC = '1'. The calibration state can be read from register CSTAT.
26 Reserved
Time Quanta per Bit Time
27:31
Configures the number of time quanta per bit time. Same value as configured in the attached
TQBT M_CANs. The range of the resulting time quanta clock cu_tqc is from 0,5 MHz (bit rate of 125 kbit/s
with 4 tq per bit time) to 25 MHz (bit rate of 1 Mbit/s with 25 tq per bit time). Valid values are 4 to 25.
1078/2058
Description
DocID027809 Rev 4
RM0400