STMicroelectronics SPC572L series Reference Manual page 606

Embedded Flash Memory (MP55)
Field
Enable High Voltage (Read/Write)
The EHV bit enables the Flash Memory module for a high voltage Program/Erase operation.
EHV is cleared on reset.
EHV must be set after an Interlock Write to start a Program/Erase sequence.
EHV may be set under one of the following conditions:
– Erase (ERS=1, ESUS=0, UT0[AIE]=0)
– Program (ERS=0, ESUS=0, PGM=1, UT0[AIE]=0)
– Erase-suspended program (ERS=1, ESUS=1, PGM=1, PSUS=0, UT0[AIE]=0).
For a program operation to initiate while an Erase is suspended, EHV must be cleared while
in Erase-Suspend (after DONE transitions to 1) before setting PGM.
In normal operation, a 1–0 transition of EHV with DONE high, PSUS low and ESUS low
terminates the current Program/Erase high voltage operation.
In an erase-suspended program operation, a 1–0 transition of EHV with DONE, ESUS, PGM
and ERS high and PSUS low terminates the program that is the current high voltage
operation.
When an operation is aborted, there is a 1–0 transition of EHV with DONE low and the
31
eventual Suspend bit for the current program/erase operation low.
EHV
An Abort causes the value of PEG to be cleared, indicating failed Program/Erase. Address
locations being operated on by the aborted operation contain indeterminate data after an
Abort. EHV cannot be set to '1' after an Abort request (EHV being cleared) until the Abort
sequence is completed (DONE transitions to 1). Once the Abort sequence is completed
(DONE=1) a new operation of the kind aborted can start provided that a new interlock is given
and then EHV is set to '1' again.
A suspended operation cannot be aborted.
Aborting a high voltage operation leaves the Flash Memory module addresses in an
indeterminate data state. This may be recovered by executing an Erase on the affected
blocks.
EHV may be written during Suspend. EHV must be high to exit Suspend, resuming previously
suspended command. EHV cannot not be written during transition into Suspend state (after
Suspend bit (ESUS or PSUS) is set high) until DONE transitions to '1'. EHV may not be
written after ESUS is set and before DONE transitions high. EHV may not be cleared after
ESUS is cleared and before DONE transitions low.
0 Flash is not enabled to perform a high voltage operation.
1 Flash is enabled to perform a high voltage operation.
A number of MCR bits are protected against Write when another bit, or set of bits, are in a
specific state. These Write locks are covered on a bit-by-bit basis in the preceding
description, but those locks do not consider the effects of trying to write two or more bits
simultaneously.
The Flash Memory module does not allow the user to write bits simultaneously (which puts
the device into an illegal state). This is implemented through a priority mechanism among
the bits shown in
606/2058
Table 298. MCR field descriptions(Continued)
Table 299.
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Description
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