External Debug Resource Allocation Control (Edbrac0) Register - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
Bit Name
17:20 — Reserved
External Debug Event 1 Debug Event
21 DEVT1
Set to 1 if a DEVT1 debug event occurred
External Debug Event 2 Debug Event
22 DEVT2
Set to 1 if a DEVT2 debug event occurred
Performance Monitor Interrupt Debug Event
23 PMI
Set to 1 if a Performance Monitor Interrupt event occurred with PMGC0
24 — Reserved
Critical Interrupt Taken Debug Event
25 CIRPT
Set to 1 if a Critical Interrupt Taken debug event occurred.
Critical Return Debug Event
26 CRET
Set to 1 if a Critical Return debug event occurred
VLE Status
27 VLES
Set to 1 if an ICMP, BRT, TRAP, RET, CRET, IAC, or DAC debug event occurred on a
PowerISA VLE Instruction. Undefined for IRPT, CIRPT, DEVT[1,2], and UDE events
Data Address Compare Offset
Indicates offset-1 of saved DSRR0 value from the address of the load or store instruction
28:30 DAC_OFST
that took a DAC Debug exception, unless a simultaneous DSI error occurs, in which case
this field is set to 3'b000 and DBSR
DAC. A DVC DAC may set this field to any value.
31 — Reserved
57.3.2.10 Debug Data Effective Address Register (DDEAR)
The Debug Data Effective Address Register (DDEAR) contains address information for data
address compare debug events (DAC). DDEAR is update by hardware with the effective
address of the load or store operation when a data address compare event is recorded in
DBSR if the previous values of the DBSR
performed, these bits must be cleared by software prior to another DDEAR hardware update
occurring. A subsequent DAC event will not update the DDEAR register if either of the
DBSR
DAC{R,W}
The DDEAR register is shown in
0 1 2 3 4 5 6
Figure 997. Debug Data Effective Address Register (DDEAR)
57.3.3

External Debug Resource Allocation Control (EDBRAC0) register

The External Debug Resource Allocation Control Register (EDBRAC0) controls resource
allocation when EDBCR0
hardware debugger to share certain debug resources with software. Individual resources
1676/2058
Table 947. DBSR field descriptions (Continued)
bits are set, in order to capture the first event address.
Data Effective Address
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 600; Read/Write; Reset - unaffected
is set to '1'. EDBRAC0 provides a mechanism for the
EDM
DocID027809 Rev 4
Description
is set to 1. Normally set to 3'b000 by a non-DVC
IDE
bits are zero. Once a DDEAR update is
DAC{R,W}
Figure 997.
RM0400
=1
UDI