Table 645. After Sck Delay Computation Example - STMicroelectronics SPC572L series Reference Manual

RM0400
the CTARx registers select the After SCK Delay by the formula in the ASC field description.
Table 645
f
P
100 MHz
PCASC and ASC fields have no effect in TSB configuration.
Note: The clock frequency mentioned in
chapter for the frequency used to drive this module in the device.
46.5.5.4 Delay after transfer (t
The delay after transfer is the minimum time between negation of the PCS signal for a frame
and the assertion of the PCS signal for the next frame. See
the delay after transfer. the PDT and DT fields in the CTARx registers select the Delay after
Transfer by the formula in the DT field description.
compute the delay after transfer.
f
P
100 MHz
Note: The clock frequency mentioned in
chapter for the frequency used to drive this module in the device.
When in non-continuous clock mode the t
specified in the CTAR[DT] bitfield description. When in continuous clock mode and TSB is
not enabled, the delay is fixed at 1 SCK period.
In TSB mode, the Delay after Transfer is equal to a number formed by concatenation of PDT
and DT fields plus 1 of the SCK clock periods. See detailed information on
Timed Serial Bus
46.5.5.5 Peripheral Chip Select Strobe Enable (PCSS)
The PCSS signal provides a delay to allow the PCS signals to settle after a transition
occurs, thereby avoiding glitches. When the DSPI is in master mode and the PCSSE bit is
set in the MCR, PCSS provides a signal for an external demultiplexer to decode the
PCS[0]–PCS[4]and PCS[6]–PCS[7] signals into as many as 128 glitch-free PCS signals.
Figure 618
shows an example of how to compute the After SCK delay.

Table 645. After SCK delay computation example

PASC Prescaler
0b01
)
DT
Table 646. Delay after transfer computation example
PDT Prescaler
0b01 3
(TSB).
shows the timing of the PCSS signal relative to PCS signals.
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
ASC
3 0b0100
Table 645 is given as an example. Refer to the clocking
Table 646
DT Scaler
0b1110 32768
Table 646 is given as an example. Refer to the clocking
delay is configured according to the equation
DT
Scaler After SCK delay
32 0.96 µs
Table 646 for an illustration of
shows an example of how to
Delay after transfer
0.98 ms
Section 46.5.9:
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