Functional' Resets - STMicroelectronics SPC572L series Reference Manual

Reset Generation Module (MC_RGM)
The status flag associated with the external reset falling edge event (RGM_FES.F_ESR0
bit) is set when the external reset is asserted and the power-on reset is not asserted.
The external reset can optionally be disabled by writing bit RGM_FERD.D_ESR0.
Note: The RGM_FERD register can be written only once between two 'destructive' reset events.
An enabled external reset normally triggers a reset sequence starting from the beginning of
PHASE1. Nevertheless, the RGM_FESS register enables the further configuring of the
reset sequence triggered by the external reset. When RGM_FESS.SS_ESR0 is set, the
external reset triggers a reset sequence starting directly from the beginning of PHASE3,
skipping PHASE1 and PHASE2. This can be useful especially when an external reset
should not reset the flash.
The MC_RGM may also assert the external reset if the reset sequence was triggered by
one of the following:
•
a power-on reset
•
a 'destructive' reset event
•
an external reset event, if configured via the RGM_FBRE register to assert the external
reset
•
a 'functional' reset event configured via the RGM_FBRE register to assert the external
reset
In this case, ESR0 is asserted until all conditions for exiting PHASE3 have been met with
the exception of the ESR0 assertion check.
If the OPT_RGM_ESR0_HW bit of the "UTEST Miscellaneous" DCF client is set to '0', the
MC_RGM contiues to assert ESR0 until the EROEC bit in the RGM_EROEC register has
been cleared by software.
In addition, the MC_RGM asserts ESR0 while the start-up self test is being executed.
The ESR0 input is disabled immediately as of the ESR0 output being asserted in order to
prevent a falling edge from being detected while the pin is being driven from the chip. The
input is then re-enabled 4 µs after the ESR0 output stops being driven by the chip in order to
allow the pull-up on the pin to take effect.
If ESR0 is stopped being asserted by the MC_RGM and the 4 µs input mask period expires
during the reset IDLE phase (e.g., due to the EROEC bit being cleared by software), and
now a low value is detected on ESR0, an external reset falling edge event does not occur,
and no new reset sequence is triggered. For a new reset sequence to trigger, ESR0 must
first be deasserted.
51.4.4

'Functional' resets

A 'functional' reset indicates that an event has occurred after which it can be guaranteed
that critical register and memory content is still intact.
The status flag associated with a given 'functional' reset event
(RGM_FES.F_<functional reset> bit) is set when the 'functional' reset is asserted and the
power-on reset is not asserted. It is possible for multiple status bits to be set simultaneously,
and it is software's responsibility to determine which reset source is the most critical for the
application.
A given 'functional' reset can be optionally disabled by software writing bit
RGM_FERD.D_<functional reset>.
1540/2058 DocID027809 Rev 4
RM0400