Table 927. Debug Mode Transition Status Register (Me_Dmts) Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400

Table 927. Debug Mode Transition Status Register (ME_DMTS) field descriptions

Field
0–3
PREVIOUS_MODE
4–7
Reserved
8
MPH_BUSY
9–10
Reserved
11
PMC_PROG
12
DBG_MODE
13
CCKL_PROG
14
PCS_PROG
Previous chip mode — These bits show the mode in which the chip was prior to the latest
change to the current mode.
0000 RESET
0001 TEST
0010 SAFE
0011 DRUN
0100 RUN0
0101 RUN1
0110 RUN2
0111 RUN3
1000 HALT0
1001 reserved
1010 STOP0
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
MC_ME/MC_PCU Handshake Busy indicator — This bit is set if the MC_ME has
requested a mode change from the MC_PCU and the MC_PCU has not yet completed its
power-up/down sequencing. It is cleared when the MC_PCU has power-up/down
sequencing.
0 Handshake is not busy
1 Handshake is busy
MC_PCU Mode Change in Progress indicator — This bit is set if the MC_PCU is in the
process of powering up or down power domains. It is cleared when all power-up/down
processes have completed.
0 Power-up/down transition is not in progress
1 Power-up/down transition is in progress
Debug mode indicator — This bit is set while the chip is in debug mode.
0 The chip is not in debug mode
1 The chip is in debug mode
Core Clock Enable/Disable in Progress — This bit is set while any core's clock is in the
process of being enabled or disabled.
0 No core clock is being enabled or disabled
1 A core clock is being enabled or disabled
Progressive System Clock Switching in Progress — This bit is set while the
progressive system clock switching process is in progress.
0 PCS is not in progress
1 PCS is in progress
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Mode Entry Module (MC_ME)
Description
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