RM0400
DSPI module
CTARs
DSPI0
DSPI4
1. Supports Microsecond Bus SCK and SOUT LVDS signal pairs.
6.7.4.2
Serial input for DSI mode
Serial input for the DSI mode is selected using the SIUL register
•
DSPI4 DSI0-31 is managed by MSCR656-687
•
DSPI4 DSI32-63 is managed by MSCR936-967
6.7.4.3
DSPI half duplex operation
Half duplex operation is not supported within the DSPI module, but it is configured by
connecting the SIN and SOUT together within the SIUL2 and operating the combined pad in
open drain mode. Software must ensure that the SOUT signal is passive (high) during SIN
reception. This can be done by reconfiguring the SIUL2 to disconnect the SOUT or by
writing a data frame that is all 1's.
6.7.4.4
Serialized timed I/O
The timer sources and injection pin inputs to be DSPI serialized downstream outputs are
selected through the SIUL2 Multiplexed Single Configuration Registers (MSCRs). Inversion
of these signals is also handled in the SIUL2. Refer to the Signal Description chapter for
details.
6.7.4.5
High speed and microsecond channel support
The baud rate generator in the DSPI is clocked from the peripheral clock. The DSPI module
can operate at a baud rate up to half the peripheral clock. Peripheral clock frequency
specification is 16 MHz to 120 MHz. As long as the peripheral clock is ≥ 100 MHz, 50 MHz
baud is achievable.
To support microsecond channel functionality, two pairs of LVDS pads are implemented per
DSPI. In the SIUL2_MSCR, the user can configure the desired port driving behavior (either
CMOS or LDVS) for the DSPI SOUT and CLK signals for those instances specified with
LVDS pins. Also configurable inside the SIUL2_MSCR are the input signals which should be
serialized for TSB mode.
6.7.4.6
DSPI HT External Trigger
Use of external hardware triggers are not supported.
c. The SPC572Lx I/O Signal Description and Input Multiplexing Tables are contained in a Microsoft Excel
workbook file attached to this document. Locate the paperclip symbol on the left side of the PDF window, and
click it. Double-click on the Excel file to open it and select the I/O Signal Description Table tab.
Table 45. DSPI instantiation
TX FIFO
depth
8
4
8
4
DocID027809 Rev 4
RX FIFO
PCS signals
depth
4
PCS[7:0]
4
PCS[7:0]
Device configuration
Data
LVDS support
serialization
support
Not available
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(1)
Available
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