Table 849. Uartcto Field Descriptions - STMicroelectronics SPC572L series Reference Manual

LINFlexD
Field
Reserved
0–19
Read returns 0.
Current Timeout
20–31
CTO defines the current value of the timeout counter. CTO is a read-only field. CTO is reset
CTO[11:0] every time UARTPTO is re-initialized, or UARTCTO = UARTPTO, or by hard/soft reset. When the
CTO value matches the preset value (UARTPTO), the status bit UARTSR[TO] is set.
50.4.2.25 DMA Tx Enable Register (DMATXE)
This register enables the DMA TX interface. This register can be written and read by
software any time.
(GCR address)
Address:
0 1
R 0 0
W
Reset 0 0
16 17
R
W
Reset 0 0
1
Depends on no_of_filters. Refer to device configuration chapter to see the number of filters used in the
device.
Field
Reserved
0 –
Read returns 0.
(2**TX_CH_NU
M–1)
Note: Refer to the device configuration chapter for the value of TX_CH_NUM used in this device.
DMA Tx channel Y enable
0 DMA Tx channel Y disabled
1 DMA Tx channel Y enabled
(2**TX_CH_NU
M) – 31
DTE[2**TX_CH_
Note: The actual size of the register DMATXE depends on the value of the static parameter
(1)
NUM–1:0]
Note: Refer to the device configuration chapter for the value of TX_CH_NUM used in this device.
1. ** stands for exponentiation.
1492/2058

Table 849. UARTCTO field descriptions

1
+0Ch
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
Figure 869. DMA Tx Enable Register (DMATXE)
Table 850. DMATXE field descriptions
TX_CH_NUM. When DMATXE = 0x00000000, the DMA TX interface FSM is forced (soft
reset) in Idle state.
DocID027809 Rev 4
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
DTE
0 0 0 0
Description
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
RM0400
14 15
0 0
0 0
30 31
0 0