Flash Memory Controller (Pflash Controller) - STMicroelectronics SPC572L series Reference Manual

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Flash memory controller (PFLASH Controller)

28.1 Introduction
The flash memory controller has two functions:
•
It acts as an interface between the system bus (AHB-Lite 2.v6) and the flash array.
•
It serves as the interface to the on-chip overlay RAM and off-chip buddy device.
The flash memory controller supports one 32-bit AHB buses and a 128-bit read data
interface to the flash memory array. Each AHB port contains a 4-entry, 2-way set-
associative mini-cache as well as an associated controller that prefetches sequential lines of
data from the flash arrays into the mini-cache. This buffer mechanism serves to deliver flash
read data with zero-wait state response on lines that reside in the cache. AHB requests that
miss the cache generate the needed flash array access and are forwarded to the AHB upon
completion. Each mini-cache entry is 128 bits in size, matching the code flash array page
size and providing 128 bytes of high-speed local storage.
28.2 Features
The following list summarizes the key features of the flash memory controller:
•
One 32-bit AHB interface ports (p0).
•
128-bit read data bus + 64-bit write data bus
•
Configurable read buffering and line prefetching support via 4-entry, 2-way set-
associative mini-cache plus prefetch controller per AHB port to provide single-cycle
"buffer hit" read response
•
Configurable access control based on read/write and AHB master ID attributes
•
Configurable access timing (wait-state programmable) allowing use in a wide range of
frequency targets
•
Support for reporting of single- and multi-bit flash ECC events on a 64-bit doubleword
boundary
•
Configurable overlay remapping of logical flash accesses to on-chip calibration RAM,
extended off-chip calibration RAM or on-chip system RAM
•
Nexus trace stream interface support for message dumping to the on-chip overlay
RAM
28.3 Block diagrams
Figure 237
flash array.
Note: This module is also known as the Platform Flash controller, that is, PFlash or
PFLASH_MP55.
e. The term "buddy device" refers to an optional companion chip with additional memory and debug features that
is paired with a production chip during system development. It is not used in production devices.
provides a block diagram showing the flash memory controller and the attached
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Flash memory controller (PFLASH Controller)
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