Table 243. System Clock Select Status Register (Cgm_Sc_Ss) Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Clock Generation Module (MC_CGM)
24.3.1.11 System Clock Select Status Register (CGM_SC_SS)
This register provides the current system clock source selection.
Address 0x07E4
0 1 2
R 0 0 0
W
Reset 0 0 0
16 17 18
R 0 0 0
W
Reset 0 0 0
Figure 191. System Clock Select Status Register (CGM_SC_SS)

Table 243. System Clock Select Status Register (CGM_SC_SS) field descriptions

Field
0–3 Reserved
System Clock Source Selection Status — This value indicates the current source for the system
clock.
0000 16 MHz internal RC oscillator (IRCOSC)
0001 external crystal oscillator (XOSC)
0010 PLL0 PHI
0011 PLL0 PHI1
0100 reserved
0101 reserved
4–7
0110 reserved
0111 reserved
SELSTAT
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 system clock is disabled
8–11 Reserved
Switch Trigger cause — This value indicates the cause for the latest clock source switch.
000 reserved
001 switch after request from MC_ME succeeded
010 switch after request from MC_ME failed due inactive target clock
12–14
011 switch after request from MC_ME failed due inactive current clock
100 switch to 16 MHz internal RC oscillator (IRCOSC) due to SAFE mode request or reset succeeded
SWTRG
101 switch to 16 MHz internal RC oscillator (IRCOSC) due to SAFE mode request or reset succeeded,
but current clock source was inactive
110 reserved
111 reserved
506/2058
3 4 5 6
0 SELSTAT
0 0 0 0
19 20 21 22
0 0 0 0
0 0 0 0
DocID027809 Rev 4
Access: User read, Supervisor read, Test read
7 8 9 10
0 0 0
0 0 0 0
23 24 25 26
0 0 0 0
0 0 0 0
Description
RM0400
11 12 13 14
0 SWTRG
0 1 0 0
27 28 29 30
0 0 0 0
0 0 0 0
15
SWIP
0
31
0
0