Clocking
Module Clock
SENT (1)
BIU
Protocol Clock
Module Clock
LINFlexD (3)
BIU
Module Clock
DSPI_0
BIU
Module Clock
DSPI_4
BIU
Module Clock
M_CAN (2)
BIU
Protocol Clock
Module Clock
BIU
PIT
r/w_data
SWT_3
SWT_2
STM_2
21.6.1
LFAST clocking
The LFAST is clocked with a 320 MHz clock signal (4 phases) coming from PLL0.
470/2058
Figure 163. Clock distribution
1
SENT_CLK
1
LIN_CLK
3
3
DSPI1_CLK
DSPI0_CLK
2
CAN_CLK
IP Bus
Clock Sync
Bridge
SIUL2
filter clk
MC_ME
MC_PCU
MC_RGM
WKPU
SSCM
BAF
DocID027809 Rev 4
sys_clk
aei_clock (BIU)
BIU
XBAR_CLK
Ext. Modulator Clock
SD_CLK
Digital I/F (1)
BIU
SAR_CLK
SARADC
Digital I/F (3)
BIU
Module Clock
FEC Clock
Module Clock
BIU
RX_CLK
TX_CLK
Ethernet
Module Clock
BIU
RF_REF
320 MHz (4 phases)
LFAST_CLK
Module Clock
BIU
ips_sync
BIU
array
XBAR_CLK
RM0400
RAM
GTM
SDADC
SDADC
1
SAR
ADC
3
Decimation
Unit
RMII
Gasket
FEC_REF_CLK
LFAST
DMA
Flash
Memory
SRAM
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