Table 939. Dbcr0 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Core Debug Support
Bit Name
External Debug mode. This bit is read-only by software. When external debug mode is enabled,
hardware-owned resources in debug registers are not affected by processor reset p_reset_b.
This allows the debugger to set up hardware debug events that remain active across a
processor reset.
0 External debug mode disabled. Internal debug events not mapped into external debug events.
1 External debug mode enabled. Hardware-owned debug events will not cause the CPU to
vector to interrupt code. Software is not permitted to write to debug registers {DBCR0–8,
IAC1–8, DAC1–4, DVC1–2[U]} unless permitted by settings in EDBRAC0. Hardware-owned
0 EDM
events will set status bits in EDBSR0.
Programming Notes:
It is recommended that debug status bits in the Debug Status Registers be cleared before
disabling external debug mode to avoid any internal imprecise debug interrupts.
Software may use this bit to determine if external debug has control over the debug registers.
The hardware debugger must set the EDM bit to '1' before other bits in this register (and other
debug registers) may be altered. On the initial setting of this bit to '1', all other bits are
unchanged. This bit is only writable through the OnCE port.
Internal Debug mode
0 Debug exceptions are disabled. Debug events do not affect DBSR.
1 IDM
1 Debug exceptions are enabled. Enabled debug events owned by software will update the
DBSR. If MSR
event in the Debug Status Register when MSR
Reset Control
00 No function
01 p_dbrstc[1] pin asserted by Debug Reset Control. Allows external device to initiate
2:3 RST
10 p_dbrstc[0] pin asserted by Debug Reset Control. Allows external device to initiate
11 Reserved
Instruction Complete Debug Event Enable
4 ICMP
0 ICMP debug events are disabled
1 ICMP debug events are enabled
Branch Taken Debug Event Enable
5 BRT
0 BRT debug events are disabled
1 BRT debug events are enabled
Interrupt Taken Debug Event Enable
6 IRPT
0 IRPT debug events are disabled
1 IRPT debug events are enabled
Trap Taken Debug Event Enable
7 TRAP
0 TRAP debug events are disabled
1 TRAP debug events are enabled
Instruction Address Compare 1 Debug Event Enable
8 IAC1
0 IAC1 debug events are disabled
1 IAC1 debug events are enabled
Instruction Address Compare 2 Debug Event Enable
9 IAC2
0 IAC2 debug events are disabled
1 IAC2 debug events are enabled
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Table 939. DBCR0 field descriptions

=1, the occurrence of a debug event, or the recording of an earlier debug
DE
processor or system reset
processor or system reset.
Description
DE
DocID027809 Rev 4
was cleared, will cause a Debug interrupt.
RM0400