Table 385. Icncmr0–Icncmr2 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface
Offset 0x0A4–0x0AC
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 341. Internal Channel Normal Conversion Mask Registers (ICNCMR0–ICNCMR2)
Field
0–31
NCE_CH[x]
Table 386. Internal Channel Normal Conversion Mask Registers to Channel
Parameter num_intch vector has positional inference for registers ICNCMR0–2, such that:
•
num_intch(i) (i = 0–31) corresponds to ICNCMR0 bit[0:31]
•
num_intch(i) (i = 32–63) corresponds to ICNCMR1 bit[0:31]
•
num_intch(i) (i = 64–95) corresponds to ICNCMR2 bit[0:31].
If any of the num_intch(i) value is '0' corresponding bit is not implemented and read access
would return '0' on that bit location. Thus:
•
If num_intch[31:0] is all 0's, register ICNCMR0 is not implemented.
•
If num_intch[63:32] is all 0's, register ICNCMR1 is not implemented.
•
If num_intch[95:64] is all 0's, register ICNCMR2 is not implemented.
In any or all of the above circumstances, the corresponding registers are treated as
reserved space and any attempt to access this space generates a transfer error.
36.5.1.14 Internal Channel Injected Conversion Mask Registers 0–2 (ICJCMR0–
ICJCMR2)
The injected conversion mask registers to channel association is described in
782/2058
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0
Table 385. ICNCMR0–ICNCMR2 field descriptions
Normal conversion enable for channel x
0 Normal conversion is disabled for CH[x].
1 Normal conversion is enabled for CH[x].
Register
ICNCMR0
ICNCMR1
ICNCMR2
DocID027809 Rev 4
6 7 8 9
NCE_CH[x]
0 0 0 0
22 23 24 25
NCE_CH[x]
0 0 0 0
Description
Association
NCE_CH[31:0]
NCE_CH[63:32]
NCE_CH[95:64]
Access: User Read/Write
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
Register bits 31:0
Table
14 15
0 0
30 31
0 0
388.