STMicroelectronics SPC572L series Reference Manual page 71

RM0400 List of figures
Figure 196. Auxiliary Clock 0 Divider 0 Configuration Register (CGM_AC0_DC0) . . . . . . . . . . . . . . . 510
Figure 197. Auxiliary Clock 0 Divider 1 Configuration Register (CGM_AC0_DC1) . . . . . . . . . . . . . . . 511
Figure 198. Auxiliary Clock 0 Divider 2 Configuration Register (CGM_AC0_DC2) . . . . . . . . . . . . . . . 512
Figure 199. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) . . . . . . . . . . . . . . . . . . . . . . . 512
Figure 200. Auxiliary Clock 1 Select Status Register (CGM_AC1_SS) . . . . . . . . . . . . . . . . . . . . . . . . 513
Figure 201. Auxiliary Clock 1 Divider 0 Configuration Register (CGM_AC1_DC0) . . . . . . . . . . . . . . . 514
Figure 202. Auxiliary Clock 2 Divider 0 Configuration Register (CGM_AC2_DC0) . . . . . . . . . . . . . . . 515
Figure 203. Auxiliary Clock 3 Select Control Register (CGM_AC3_SC) . . . . . . . . . . . . . . . . . . . . . . . 516
Figure 204. Auxiliary Clock 3 Select Status Register (CGM_AC3_SS) . . . . . . . . . . . . . . . . . . . . . . . . 517
Figure 205. Auxiliary Clock 7 Select Control Register (CGM_AC7_SC) . . . . . . . . . . . . . . . . . . . . . . . 518
Figure 206. Auxiliary Clock 7 Select Status Register (CGM_AC7_SS) . . . . . . . . . . . . . . . . . . . . . . . . 519
Figure 207. Auxiliary Clock 7 Divider 0 Configuration Register (CGM_AC7_DC0) . . . . . . . . . . . . . . . 520
Figure 208. Auxiliary Clock 8 Select Control Register (CGM_AC8_SC) . . . . . . . . . . . . . . . . . . . . . . . 520
Figure 209. Auxiliary Clock 8 Select Status Register (CGM_AC8_SS) . . . . . . . . . . . . . . . . . . . . . . . . 521
Figure 210. Auxiliary Clock 8 Divider 0 Configuration Register (CGM_AC8_DC0) . . . . . . . . . . . . . . . 522
Figure 211. Auxiliary Clock 10 Select Control Register (CGM_AC10_SC) . . . . . . . . . . . . . . . . . . . . . 523
Figure 212. Auxiliary Clock 10 Select Status Register (CGM_AC10_SS) . . . . . . . . . . . . . . . . . . . . . . 524
Figure 213. Auxiliary Clock 10 Divider 0 Configuration Register (CGM_AC10_DC0) . . . . . . . . . . . . . 525
Figure 214. Auxiliary Clock 11 Select Control Register (CGM_AC11_SC) . . . . . . . . . . . . . . . . . . . . . 526
Figure 215. Auxiliary Clock 11 Select Status Register (CGM_AC11_SS) . . . . . . . . . . . . . . . . . . . . . . 527
Figure 216. Auxiliary Clock 11 Divider 0 Configuration Register (CGM_AC11_DC0) . . . . . . . . . . . . . 528
Figure 217. Auxiliary Clock 11 Divider 1 Configuration Register (CGM_AC11_DC1) . . . . . . . . . . . . . 529
Figure 218. MC_CGM System Clock Ramp-Down Timing (k = 6 example) . . . . . . . . . . . . . . . . . . . . 532
Figure 219. MC_CGM System Clock Ramp-Up Timing (k = 6 example). . . . . . . . . . . . . . . . . . . . . . . 533
Figure 220. MC_CGM Auxiliary Clock 0 Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Figure 221. MC_CGM Auxiliary Clock 1 Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Figure 222. MC_CGM Auxiliary Clock 2 Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Figure 223. MC_CGM Auxiliary Clock 3 Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Figure 224. MC_CGM Auxiliary Clock 7 Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Figure 225. MC_CGM Auxiliary Clock 8 Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Figure 226. MC_CGM Auxiliary Clock 10 Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Figure 227. MC_CGM Auxiliary Clock 11 Generation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Figure 228. MC_CGM Fractional Division Example Waveform (divide by 2.3) . . . . . . . . . . . . . . . . . . 541
Figure 229. XOSC_CTL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Figure 230. IRCOSC Control register (IRCOSC_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Figure 231. IRCOSC Native Trimming register (IRCOSC_NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Figure 232. IRCOSC Temperature Trimming register (IRCOSC_TT) . . . . . . . . . . . . . . . . . . . . . . . . . 549
Figure 233. Simplified platform block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
Figure 234. RAM controller block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Figure 235. Platform RAM Configuration Register 1 (PRCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Figure 236. RAM word composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Figure 237. Platform-centric block diagram with PFLASH_MP55 flash memory controller . . . . . . . . . 556
Figure 238. PFLASH_MP55 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
Figure 239. PFCR1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Figure 241. PFCR3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
Figure 242. PFAPR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Figure 243. PFCRCR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Figure 244. PFCRDE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Figure 245. PFlash Calibration Region Descriptor n, Word0 (PFCRDn.Word0) . . . . . . . . . . . . . . . . . 576
Figure 246. PFlash Calibration Region Descriptor n, Word1 (PFCRDn.Word1) . . . . . . . . . . . . . . . . . 577
Figure 247. PFlash Calibration Region Descriptor n, Word2 (PFCRDn.Word2) . . . . . . . . . . . . . . . . . 577
Figure 248. Flash memory controller 4-entry, 4-way mini-cache organization. . . . . . . . . . . . . . . . . . . 581
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