Table 87. L1Sel7 Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Calibration and Debug
Field
000 CPU interrupt current priority match to C2PIS
001 CPU write to ME bits of MSR
010 Reserved
011 Reserved
MUX 54
100 Reserved
101 Reserved
110 SPU counter event 14
111 Reserved
000 Reserved
001 Reserved
010 Reserved
011 Reserved
MUX 55
100 Reserved
101 Reserved
110 SPU counter event 15
111 Reserved
Table 87
Field
000 Reserved
001 Reserved
010 Reserved
011 Reserved
MUX 56
100 Reserved
101 Reserved
110 Reserved
111 DCI EVTI0
000 Reserved
001 Reserved
010 Reserved
011 Reserved
MUX 57
100 Reserved
101 Reserved
110 Reserved
111 DCI EVTI1
000 CPU write to EE bits of MSR
001 CPU write to CE bits of MSR
010 Reserved
011 Reserved
MUX 58
100 Reserved
101 Reserved
110 Reserved
111 DCI EVTO0
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Table 86. L1SEL6 register field descriptions(Continued)
contains the L1SEL7 register field descriptions.

Table 87. L1SEL7 register field descriptions

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