Interrupt Controller (Intc) Configuration - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
0–4 Reserved
5–7
Reserved, undefined
RSV
8–12 Reserved
13–15 Reserved, undefined
RSV
16–20 Reserved
21–23 Reserved, undefined
RSV
24–28 Reserved
Pending read enable (PRE) M2
29
This bit controls the bus gasket's handling of pending read transactions.
PRE_M2
0 Pending reads are disabled.
1 Pending reads are enabled.
Burst read enable (BRE) M2
30
This bit controls the bus gasket's handling of burst read transactions.
BRE_M2
0 Burst reads are converted into a series of single transactions on the slave side of the gasket.
1 Burst reads are optimized for best system performance.
Burst write enable (BWE) M2
This bit controls the bus gasket's handling of burst write transactions.
31
0 Burst writes are converted into a series of single transactions on the slave side of the gasket.
BWE_M2
1 Burst writes are optimized for best system performance. Note this setting treats writes as
"imprecise" such that an error response on any beat of the burst is reported on the last beat.
6.3.6

Interrupt Controller (INTC) configuration

6.3.6.1 INTC implemented registers
Table 21
Address offset
000h
010h
014h
018h
020h
024h
028h
030h
Table 20. IAHB_BE2 field descriptions
shows the registers implemented on the INTC on this chip.
Table 21. INTC implemented registers
INTC Block Configuration Register (INTC_BCR)
INTC Current Priority Register for Processor (INTC_CPR0)
Reserved
Reserved
INTC Interrupt Acknowledge Register for Processor (INTC_IACKR0)
Reserved
Reserved
INTC End Of Interrupt Register for Processor (INTC_EOIR0)
DocID027809 Rev 4
Description
Register
Device configuration
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