Descriptor Individual Upper Address Register (Iaur) - STMicroelectronics SPC572L series Reference Manual

RM0400
48.4.14

Descriptor Individual Upper Address Register (IAUR)

IAUR contains the upper 32 bits of the 64-bit individual address hash table. The address
recognition process uses this table to check for a possible match with the destination
address (DA) field of receive frames with an individual DA.
This register is not reset and you must initialize it.
Offset: 118h
0 1 2 3
R
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 703. Descriptor Individual Upper Address Register (IAUR)
Field
The upper 32 bits of the 64-bit hash table used in the address recognition process for receive
IADDR1 frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1
contains hash index bit 32.
48.4.15 Descriptor Individual Lower Address Register (IALR)
IALR contains the lower 32 bits of the 64-bit individual address hash table. The address
recognition process uses this table to check for a possible match with the DA field of receive
frames with an individual DA.
This register is not reset and you must initialize it.
Offset: 11Ch
0 1 2 3
R
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Figure 704. Descriptor Individual Lower Address Register (IALR)
Field
The lower 32 bits of the 64-bit hash table used in the address recognition process for receive
IADDR2 frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2
contains hash index bit 0.
48.4.16 Descriptor Group Upper Address Register (GAUR)
GAUR contains the upper 32 bits of the 64-bit hash table used in the address recognition
process for receive frames with a multicast address.
This register is not reset and you must initialize it.
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Table 713. IAUR field descriptions
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Table 714. IALR field descriptions
DocID027809 Rev 4
Fast Ethernet Controller (FEC)
IADDR1
Description
IADDR2
Description
Access: User read/write
Access: User read/write
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