Table 798. Sdma_Ctrl Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Address Offset: 0x002C
0
R
W
Reset 0
8
R
W
Reset 0
16
R SDMA_EN1
SDMA_EN1
5
W
Reset 0
24
R
SDMA_EN7 SDMA_EN6 SDMA_EN5 SDMA_EN4 SDMA_EN3 SDMA_EN2 SDMA_EN1 SDMA_EN0
W
Reset 0
Figure 786. Slow Serial Message DMA Control Register (SDMA_CTRL)
Field
0:15 Reserved. Read returns zero
Enable DMA for Slow Serial Messages on Channels 0 to 15. These bits are writeable when
corresponding Slow Serial Message Ready Interrupt Enable bits are set to 0.
16:31
SDMA_ENn
0 – DMA for Slow Serial Messages is disabled
(n = 15 to 0)
1 – DMA for Slow Serial Messages is enabled
49.3.2.10 Fast Message Ready Interrupt Control Register (FRDY_IE)
Note: The following register figure and table shows the maximum possible configuration but the
exact number of valid register bits are dependent on supported SENT channels on the
device. Please see Device Configuration chapter for number of support SENT
channels.Reads of bits beyond the supported number of channels should be ignored and
writes to these bits are unadvisable and may cause unexpected behavior.
1 2
0 0
9 10
0 0
17 18
SDMA_EN1 SDMA_EN1
4 3
0 0
25 26
0 0

Table 798. SDMA_CTRL field descriptions

DocID027809 Rev 4
3 4
0 0
11 12
0 0
19 20
SDMA_EN1 SDMA_EN1
2 1
0 0
27 28
0 0
Description
SENT Receiver (SRX)
Access: RW
5 6
0 0
13 14
0 0
21 22
SDMA_EN9 SDMA_EN8
0
0 0
29 30
0 0
1379/2058
7
0
15
0
23
0
31
0
1410