Dspi Push Fifo Register In Master Mode (Dspi_Pushr) - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Command FIFO FIll DMA or Interrupt Request Select.
Selects between generating a DMA request or an interrupt request.
16
DSPI_SR[CMDFFF] flag and DSPI_RSER[CMDFFF_RE] must be set.
CMDFFF_DIRS
0 Interrupt request.
1 DMA request.
17–31
This read-only bitfield is reserved and always has the value zero.
Reserved
46.3.7

DSPI PUSH FIFO Register In Master Mode (DSPI_PUSHR)

PUSHR provides the means to write to the TX FIFO and CMD FIFO.
Data written to this register is transferred to:
•
The TX FIFO for 8- or 16-bit writes to the Data field of PUSHR.
•
The CMD FIFO for writes to the Command field of PUSHR.
In master mode, the register provides 16-bit command to the CMD FIFO and 16-bit data to
the TX FIFO.
In slave mode, CMD FIFO is unused and the 16-bit Command Field of PUSHR is reserved.
When Extended SPI Mode is not enabled (MCR[XSPI] = 0):
•
TX FIFO and CMD FIFO must be filled simultaneously.
•
Writes must be given to both Data and Command fields of PUSHR for every PUSHR
operation.
•
TX FIFO and CMD FIFO can be considered a single 32-bit FIFO.
When Extended SPI Mode is enabled (MCR[XSPI] = 1):
•
TX FIFO and CMD FIFO can be written independently.
•
A PUSHR Read Operation returns the topmost TX FIFO and CMD FIFO entries
concatenated.
When DSPI Module is disabled, any writes to this register do not update the FIFO. Reads
during Module disable mode return the last PUSHR write performed when Module was
enabled.
Table 618. DSPI_RSER field descriptions(Continued)
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
Description
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