STMicroelectronics SPC572L series Reference Manual page 200

Reset and Boot
This is the header file for the CPU that starts executing the user application code.
The Boot CPU header is programmed into flash memory at the same time the user
application program is programmed into flash memory. The core searches for the boot
header, which can be located at one of four addresses:
•
0x100_0000
•
0x104_0000
•
0x108_0000
•
0x10C_0000
A valid Boot Header_ID begins with the value 0x005A.
The boot header structure consists of the following words:
1. Boot Header_ID/Boot_CPU
2. Start address
To indicate a valid boot header, the 16-bit Boot_Header_ID field is written with the value
0x005A.
7.4.5.9 Valid boot header is not found (decision point N)
The Core, executing code in the BAF, enters serial boot mode to obtain an application
program as it does not find a valid boot header file in flash memory.
Note: This mode uses a defined protocol to receive a program over a serial port via the LINFlexD
port. The core then jumps to the start address of the program and begins execution.
7.4.5.10 Initialize RAM (state 35)
The core, executing code in the BAF, initializes RAM areas in preparation for serial boot
mode. This mode configures the LINFlexD port to receive code from an external source
using a basic UART protocol.
7.4.5.11 Enter serial boot mode (state 14)
Figure 27: Boot-up sequence, part D
7.4.5.12 Life Cycle check indicates FIELD (decision point G)
There are two possible settings for the Life Cycle parameter:
•
FIELD indicates that application code has been programmed into the flash memory of
the device. Serial boot mode is exited and IOP enters a 'wait' mode until a watchdog
reset occurs.
•
FACTORY means that there is no application code programmed into the flash memory.
For the present example a setting of FACTORY is assumed.
7.4.5.13 Stop—wait for watchdog (state 36)
This state is entered when the SPC572Lx's program flash memory is incorrectly
programmed.
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shows the boot loader flow.
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