Error Register Low (Dma_Errl) - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Interrupt request 5
26
0 The interrupt request for corresponding channel is cleared
INT5
1 The interrupt request for corresponding channel is active
Interrupt request 4
27
0 The interrupt request for corresponding channel is cleared
INT4
1 The interrupt request for corresponding channel is active
Interrupt request 3
28
0 The interrupt request for corresponding channel is cleared
INT3
1 The interrupt request for corresponding channel is active
Interrupt request 2
29
0 The interrupt request for corresponding channel is cleared
INT2
1 The interrupt request for corresponding channel is active
Interrupt request 1
30
0 The interrupt request for corresponding channel is cleared
INT1
1 The interrupt request for corresponding channel is active
Interrupt request 0
31
0 The interrupt request for corresponding channel is cleared
INT0
1 The interrupt request for corresponding channel is active
19.3.14

Error Register Low (DMA_ERRL)

The ERRL provides a bit map for the 16 channels, signaling the presence of an error for
each channel. ERRL covers channels 15–00. The eDMA engine signals the occurrence of
an error condition by setting the appropriate bit in this register. The outputs of this register
are enabled by the contents of the EEI, then logically summed across groups of 16 channels
to form several group error interrupt requests that are then routed to the interrupt controller.
During the execution of the interrupt-service routine associated with any DMA errors, it is
software's responsibility to clear the appropriate bit, negating the error-interrupt request.
Typically, a write to the CERR in the interrupt-service routine is used for this purpose. The
normal DMA channel completion indicators (setting the transfer control descriptor DONE
flag and the possible assertion of an interrupt request) are not affected when an error is
detected.
The contents of this register can also be polled because a non-zero value indicates the
presence of a channel error regardless of the state of the EEI. The state of any given
channel's error indicators is affected by writes to this register; it is also affected by writes to
the CERR. On writes to the ERR, a one in any bit position clears the corresponding
channel's error status. A zero in any bit position has no effect on the corresponding
channel's current error status. The CERR is provided so the error indicator for a single
channel can easily be cleared.
Table 177. DMA_INTL field descriptions(Continued)
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