Table 484. Gtmdi_Aru_Dtc Field Descriptions - STMicroelectronics SPC572L series Reference Manual

GTM Development Interface (GTMDI)
Register index: 56
31 30
R 0 0
W
RESET: 0 0
15 14
R 0 0
W
RESET: 0 0
Table 484
Field
Start/Stop input signal selection 1. Selects the Start/Stop input that is used by the ARU Debugging
Channel 0 data trace messages. These signals are actually a pair of signals.
21–20
00 SHARED_WPT_ST[0]
STSEL1 01 SHARED_WPT_ST[1]
10 SHARED_WPT_ST[2]
11 SHARED_WPT_ST[3]
Data Trace Message Control. This bit controls ARU data trace messages transmission for ARU
Debugging Channel 0. This bit is written by the JTAG interface but can also be controlled at SoC
17
level by dedicated Start/Stop signals, inputs to GTMDI.
DMC1
0 Data Trace Messages disabled
1 Data Trace Messages enabled
Start/Stop Enable 1. The SEN 1 bit field enables the ARU data trace message generator for ARU
Debugging Channel 0 to consider the Start/Stop inputs for data trace message transmission. If this
16 bit is cleared, the messages are controlled only by JTAG writes to the DMC1 Data Trace Message
Control bit in this register.
SEN1
0 Disable trace control from Start/Stop inputs
1 Enable trace control from Start/Stop inputs
Start/Stop input signal selection 2. Selects the Start/Stop input that is used by the ARU Debugging
Channel 1 data trace messages. These signals are actually a pair of signals.
5–4
00 SHARED_WPT_ST[0]
STSEL2 01 SHARED_WPT_ST[1]
10 SHARED_WPT_ST[2]
11 SHARED_WPT_ST[3]
918/2058
29 28 27 26
0 0 0 0
0 0 0 0
13 12 11 10
0 0 0 0
0 0 0 0
Figure 431. ARU data trace control register (GTMDI_ARU_DTC)
describes the GTMDI_ARU_DTC register functions.

Table 484. GTMDI_ARU_DTC field descriptions

DocID027809 Rev 4
25 24 23 22
0 0 0 0
0 0 0 0
9 8 7 6
0 0 0 0
0 0 0 0
Description
21 20 19 18
0 0
STSEL1
0 0 0 0
5 4 3 2
0 0
STSEL2
0 0 0 0
RM0400
17 16
DMC1 SEN1
0 0
1 0
DMC2 SEN2
0 0