Table 532. Bit Timing And Prescaler Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Address: 0x001C
0 1
R 0 0
W
Reset 0 0
16 17 18
R 0 0
W
Reset 0 0
1. These are protected write (P) bits which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0
[INIT] of CCCR register are set to "1".
Field
0:5 Reserved
Baud Rate Prescaler
(0x000–0x3FF) The value by which the oscillator frequency is divided for generating the bit time
6:15
quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate
BRP
Prescaler are 0 to 1023. The actual interpretation by the hardware of this value is such that one
more than the value prog rammed here is used.
16:17 Reserved
Time segment before sample point
18:23
(0x01–0x3F) Valid values are 1 to 63. The actual interpretation by the hardware of this value is
TSEG1
such that one more than the prog rammed value is used.
The time segment before the sample point
24:27
(0x0–0xF) Valid values are 0 to 15. The actual interpretation by the hardware of this value is such
TSEG2
that one more than the prog rammed value is used.
(Re) Synchronization Jump Width
28:31
(0x0–0xF) Valid values are 0 to 15. The actual interpretation by the hardware of this value is such
SJW
that one more than the value prog rammed here is used.
Note: With a CAN clock of 8 MHz, the reset value of 0x00000A33 configures the M_CAN for a bit
rate of 500 kbit/s.
Note: The Information Processing Time (IPT) of the M_CAN is 0 tq. Therefore, to conform to the
CAN protocol specification, the lengths for phase segment 1 (Phase_Seg1) and phase
segment 2 (Phase_Seg2) must be equal.
2 3 4 5
0 0 0 0
0 0 0 0
19 20 21
1
TSEG1
0 0 1 0
Figure 478. Bit Timing and Prescaler Register

Table 532. Bit Timing and Prescaler Field Descriptions

6 7 8 9
0 0 0 0
22 23 24 25
TSEG2[3:0]
1 0 0 0
Description
DocID027809 Rev 4
CAN Subsystem
Access: Read Protected
10 11 12 13
(1)
BRP
0 0 0 0
26 27 28 29
1
SJW
1 1 0 0
14 15
0 0
30 31
1
1 1
1011/2058
1091