Table 381. Icdsr0–Icdsr2 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Interface
Field
0–31
DS_CH[x]
f Table 382. Internal Channel DMA Select Registers to Channel Association
36.5.1.11 Watchdog Threshold Registers 0–3 (WTHRHLR0–WTHRHLR3)
Offset 0x060–0x06C
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Figure 339. Watchdog Threshold Registers 0–3 (WTHRHLR0–WTHRHLR3)
Field
0–3
4–15
THRH
16–19
20–31
THRL
The number of WTHRHLR registers depends on num_watchdog generic parameter
configuration. If num_watchdog is zero, these registers are not implemented.
The length of the threshold field depends on the generic resolution.
780/2058
Table 381. ICDSR0–ICDSR2 field descriptions
DMA select for channel x
0 CH[x] is disabled to transfer data in DMA mode.
1 CH[x] is enabled to transfer data in DMA mode.
Register
ICDSR0
ICDSR1
ICDSR2
2 3 4 5
0 0
0 0 1 1
18 19 20 21
0 0
0 0 0 0
Table 383. WTHRHLR0–WTHRHLR3 field descriptions
Reserved
Write of any value has no effect; read value is always 0.
High threshold value for channel x
Reserved
Write of any value has no effect; read value is always 0.
Low threshold value for channel x
DocID027809 Rev 4
Description
DS_CH[31:0]
DS_CH[63:32]
DS_CH[95:64]
6 7 8 9
THRH
1 1 1 1
22 23 24 25
THRL
0 0 0 0
Description
Register bits 31:0
Access: User Read/Write
10 11 12 13
1 1 1 1
26 27 28 29
0 0 0 0
14 15
1 1
30 31
0 0