Table 262. Auxiliary Clock 8 Divider 0 Configuration Register (Cgm_Ac8_Dc0) Field Descriptions - STMicroelectronics SPC572L series Reference Manual

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Table 262. Auxiliary Clock 8 Divider 0 Configuration Register (CGM_AC8_DC0) field descriptions

Field
Divider Enable
0
0 Disable auxiliary clock 8 divider 0
DE
1 Enable auxiliary clock 8 divider 0
1–9
Reserved
Divider Division Value — The resultant CCCU clock will have a period 'DIV + 1' times that of auxiliary clock
10–15
8. If DE is set to 0 (divider 0 is disabled), any write access to the DIV field is ignored and the CCCU clock
DIV
remains disabled.
16–31
Reserved
24.3.1.31 Auxiliary Clock 10 Select Control Register (CGM_AC10_SC)
Address 0x0940
0
1
2
R
0
0
0
W
Reset
0
0
0
16
17
18
R
0
0
0
W
Reset
0
0
0
Figure 211. Auxiliary Clock 10 Select Control Register (CGM_AC10_SC)
This register is used to select the current clock source for the for the following clocks:
undivided: (unused)
divided by auxiliary clock 10 divider 0: FEC reference clock
See
Figure 226
for details.
Access: User read/write, Supervisor read/write, Test read/write
3
4
5
6
0
SELCTL
0
0
1
1
19
20
21
22
0
0
0
0
0
0
0
0
DocID027809 Rev 4
Clock Generation Module (MC_CGM)
Description
7
8
9
10
0
0
0
0
0
0
0
23
24
25
26
0
0
0
0
0
0
0
0
11
12
13
14
0
0
0
0
0
0
0
0
27
28
29
30
0
0
0
0
0
0
0
0
523/2058
15
0
0
31
0
0
541

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