RM0400
Decorated Storage Memory Controller (DSMC)
Figure 275. DSMC Block Diagram
s_hrdata
m_haddr
m_hwchkbit
s_hrchkbit
m_hwdata
ecc_hmatrix32
ecc_hmatrix64
ecc_hmatrix64
1
1
1
m_multi_ecc_err
s_multi_ecc_err
ecc_hmatrix64_i
ecc_detect64
ecc_hmatrix64_i
ecc_detect64
m_single_ecc_err
s_single_ecc_err
hwdata[63:0]
{ hrchkbit[7:0], hrdata[63:0] }
m_hdec*, m_hsiz, m_haddr
hrdata[63:0]
1
DSMC
0
Operation
ctl
m_hwdata[63:0]
zero_result_mask[63:0]
ecc_hmatrix64
0
s_hwdata[63:0]
hrchkbit_reg[7:0]
ctl
m_hwchkbit[7:0]
m_hrdata[63:0]
s_hwchkbit[7:0]
DocID027809 Rev 4
647/2058
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