Reserved Registers (Reserved) - STMicroelectronics SPC572L series Reference Manual

RM0400
57.5.9.5 Machine State Register (MSR)
The MSR is a 32-bit register used to read/write the Machine State Register. Whenever the
external command controller needs to save or modify the contents of the Machine State
Register, this register is used.This register is affected by the operations performed during
the debug mode and must be restored by the external command controller when returning
to normal mode.
57.5.9.6 Exiting Debug mode and interrupt blocking
When exiting debug mode with a Go+Exit, "asynchronous" interrupts are blocked until the
first instruction to be executed begins execution. This includes External and Critical input,
NMI, and machine check interrupts. Asynchronous debug interrupts are not blocked
however, and the CPU will reenter debug mode without executing an instruction following
Go+Exit, although it may fetch an instruction and discard it. Exceptions due to an illegal
instruction or error flags set within the CPUSCR CTL register are not blocked, since they
apply to the instruction in the CPUSCR IR.
57.5.10

Reserved registers (Reserved)

The reserved registers are used to control various test control logic. These registers are not
intended for customer use. To preclude device and/or system damage, these registers
should not be accessed.
57.6 Watchpoint support
e200z215An3 supports the generation and signalling of watchpoints when operating in
internal debug mode (DBCR0
Watchpoints are indicated with a dedicated set of interface signals. The jd_watchpt[0:31]
output signals are used to indicate that a watchpoint has occurred. Certain watchpoints
however (DEVENT-based, DTC-based, and Performance Monitor watchpoints) are not
qualified with EDBCR0
Each debug address compare function (IAC1–8, DAC1–4), as well as other event types are
capable of triggering a watchpoint output. The DBCRx control fields are used to configure
watchpoints, regardless of whether events are enabled in DBCR0. Watchpoints may occur
whenever an associated event would have been posted in the Debug Status Register if
enabled. No explicit enable bits are provided for watchpoints; they are always enabled by
definition, although the data address compare watchpoints may be controlled for read and
write accesses via configuration fields in DBCR4, 7, and 9. During a debug session, debug
events (other than PMI, DEVT1 and DEVT2) with a corresponding DBSR bit are blocked
from asserting a watchpoint. The Performance Monitor, DEVNT-based and DTC-based
watchpoints are not blocked during a debug session. If not desired, for address-based
events the base address values for these events may be programmed to an unused system
address. MSR
External logic may monitor the assertion of these signals for debugging or triggering
purposes. Watchpoints are signaled in the clock cycle following the occurrence of the actual
event. The Nexus3 module also monitors assertion of a portion of these output signals
(jd_watchpt[0:31]) for various development control purposes. (See the "Watchpoint Trace
Messaging" section in the Core (e200z215An3) Nexus 3 Module chapter.)
Note that these signals are m_clk domain signals, not j_tclk domain signals.
=1) or in external debug mode (EDBCR0
IDM
or DBCR0
EDM
has no effect on watchpoint generation.
DE
DocID027809 Rev 4
e200z215An3 Core Debug Support
.
IDM
=1).
EDM
1715/2058
1719