Figure 915. Peripheral Reset Register 4 (Rgm_Prst4) - STMicroelectronics SPC572L series Reference Manual

RM0400
Table 869. Peripheral Reset Registers (RGM_PRST3) Field Descriptions(Continued)
Field
28
DSPI_0_RST
29
30
DSPI_4_RST
31
51.3.1.16 Peripheral Reset Register 4 (RGM_PRST4)
This register provides individual resets for various peripherals. Supervisor and test modes
allow for read/write access, whereas read access only is allowed in user mode.
Caution: Use the RGM_PRST4 register with care. See <Cross Refs>Section 51.4.7, Individual
peripheral resets for the proper sequence to prevent unexpected chip behavior.
Address 0x620
0 1 2
R 0 0 0
W
Reset 0 0 0
16 17 18
R 0 0 0
W
Reset 0 0 0
Peripheral reset — Writing a '1' to this bit will reset the corresponding peripheral. Writing a
'0' to this bit will release the reset to the corresponding peripheral if the bit's current value is
'1', otherwise it will have no effect.
0 no forced reset of peripheral
1 forced reset of peripheral
Reserved
Peripheral reset — Writing a '1' to this bit will reset the corresponding peripheral. Writing a
'0' to this bit will release the reset to the corresponding peripheral if the bit's current value is
'1', otherwise it will have no effect.
0 no forced reset of peripheral
1 forced reset of peripheral
Reserved
3 4 5
0 0 0
0 0 0
19 20 21
0 0 0
0 0 0

Figure 915. Peripheral Reset Register 4 (RGM_PRST4)

DocID027809 Rev 4
Reset Generation Module (MC_RGM)
Description
Access: User read, Supervisor read/write, Test read/write
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
0 0 0 0
14 15
0 0
0 0
30 31
0
0 0
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1542