Figure 460. Data Write Message Format - STMicroelectronics SPC572L series Reference Manual

RM0400
42.6.8.1 MCS data write message
The MCS data write message contains the data write value and the address of the RAM
target location. The data write message format is shown in
6 bits K bits
TCODE (56) SRC
42.6.8.2 MCS data read message
The MCS data read message contains the data read value and the address of the RAM
target location. The data read message format is shown in
6 bits K bits
TCODE (57) SRC
42.6.8.3 MCS data trace operation
Data tracing is performed by snooping a dedicated MCS/Nexus interface for RAM read and
write cycles. Data trace functions are enabled by setting the appropriate fields in the
following registers:
•
MCSx Development Control (GTMDI_MCSx_DC) Register
•
MCSx Data Trace Control (GTMDI_MCSx_DTC) Register
•
MCSx Data Trace Address Range (GTMDI_MCSx_DTAR) Register
For details on register configuration, refer to
MCSx data tracing have independent Data Trace Address Range registers which allows
more flexibility. An Error condition may occur in case of Queue full event. Data trace flow is
depicted in

Figure 460. Data write message format

1 bit
MCSN
Length = 56+K bits
Figure 461. Data read message format
1 bit
MCSN
Length = 56+K bits
Figure 462.
DocID027809 Rev 4
GTM Development Interface (GTMDI)
Figure
3 bits 14 bits
CHN ADDR
Figure
3 bits 14 bits
CHN ADDR
Section 42.5.1, Register
460.
32 bits
DATA
461.
32 bits
DATA
descriptions. The
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