Table 695. Fec Sub-Block Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Block
Control and status
Provides global control (Ethernet reset and enable) and interrupt managing registers
registers (CSR)
A RISC-based controller providing these functions in the FEC:
– Initialization (those internal registers not initialized by you or hardware)
– High-level control of the DMA channels (initiating DMA transfers)
Descriptor controller
– Interpreting buffer descriptors
– Address recognition for receive frames
– Random number generation for transmit collision backoff timer
Provides multiple channels allowing transmit data, transmit descriptor, receive data and
receive descriptor accesses to all run independently
DMA block
Note: In this document, "DMA" refers to the DMA block within the FEC, and is not related to
Provides a serial channel for control/status communication with the external physical layer
device (transceiver). This serial channel consists of:
Media independent
interface (MII) – The management data clock (FEC_MDC)
– The management data input/output lines (FEC_MDIO) of the MII interface
Maintains counters for a variety of network events and statistics. It is not necessary for
operation of the FEC, but provides valuable counters for network management. The
counters supported are:
Message information
– The RMON (RFC 1757) Ethernet Statistics group
block (MIB)
– Some of the IEEE 802.3 counters
See the memory map for more information.
Serves as the focal point of all data flow in the Fast Ethernet controller and divides into
transmit and receive FIFOs. The FIFO boundaries are programmable using the FRSR
register.
RAM
User data flows to/from the DMA block from/to the receive/transmit FIFOs.
Transmit data flows from the transmit FIFO into the transmit block.
Receive data flows from the receive block into the receive FIFO.
Transmit and receive
Provide the Ethernet MAC functionality (with some assist from microcode)
blocks

Table 695. FEC sub-block descriptions

any other DMA controllers that may be present on the chip.
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Fast Ethernet Controller (FEC)
Description
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