STMicroelectronics SPC572L series Reference Manual page 976

GTM101 Integration (GTMINT) Module
Offset
0x1C000
–
0x1DFFC
0x1E000 – 0x27FFC
0x28000 Control Register 0 (DPLL_CTRL_0
0x28004 Control Register 1 (DPLL_CTRL_1)
Control Register 2 (actions 0–7 enable)
0x28008
(DPLL_CTRL_2)
Control Register 3 (actions 8–15 enable)
0x2800C
(DPLL_CTRL_3)
Control Register 4 (actions 16–24 enable)
0x28010
(DPLL_CTRL_4)
Control Register 5 (actions 16–24 enable)
0x28014
(DPLL_CTRL_5)
ACTION Status Register with connected
0x28018
shadow register (DPLL_ACT_STA)
Offset and switch old/new address register
0x2801C
(DPLL_OSW)
Address offset register for APT in RAM
0x28020
region 2 (DPLL_AOSV_2)
Actual RAM pointer to RAM regions 2a, b
0x28024
and d (DPLL_APT)
Actual RAM pointer to regions 1c1, 1c2 and
0x28028
1c4 (DPLL_APS)
Actual RAM pointer to RAM region 2c
0x2802C
(DPLL_APT_2c)
Actual RAM pointer to RAM region 1c3
0x28030
(DPLL_APS_1c3)
Number of recent TRIGGER events used for
0x28034 calculations (mod 2*(TNU +1-SYN_NT))
(DPLL_NUTC)
Number of recent STATE events used for
0x28038 calculations (mod 2*(SNU +1-SYN_NS)
(DPLL_NUSC)
Number of active TRIGGER events to
0x2803C
interrupt (DPLL_NTI_CNT)
Interrupt notification register
0x28040
(DPLL_IRQ_NOTIFY)
0x28044 Interrupt enable register (DPLL_IRQ_EN)
976/2058
Table 516. GTMINT module memory map(Continued)
Use
Reserved for F2A1, AFD1, FIFO1, and FIFO1 MEM
Digital PLL Module (DPLL)
DocID027809 Rev 4
Access Reset value
Reserved
R/W 0x003B_BA57 See GTM Spec.
R/W 0xB000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0200
R/W 0x1810_0800
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0001_2001
R/W 0x0000_2081
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
RM0400
(1)
Location
2
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.