Table of Contents
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Enhanced Direct Memory Access (eDMA)
Absolute
address
(hex)
Channel 13 Master ID Register
FC0A_014D
(DMA_DCHMID13)
Channel 14 Master ID Register
FC0A_014E
(DMA_DCHMID14)
Channel 15 Master ID Register
FC0A_014F
(DMA_DCHMID15)
FC0A_0150–
Reserved
FC0A_0FFF
TCD0 Source Address
FC0A_1000
(DMA_TCD0_SADDR)
TCD0 Transfer Attributes
FC0A_1004
(DMA_TCD0_ATTR)
TCD0 Signed Source Address Offset
FC0A_1006
(DMA_TCD0_SOFF)
TCD0 Minor Byte Count (Minor Loop
Disabled)
(DMA_TCD0_NBYTES_MLNO)
FC0A_1008
(DMA_TCD0_NBYTES_MLOFFNO)
(DMA_TCD0_NBYTES_MLOFFYES)
FC0A_100C (DMA_TCD0_SLAST)
FC0A_1010 (DMA_TCD0_DADDR)
(DMA_TCD0_CITER_ELINKYES)
TCD0 Current Minor Loop Link, Major
FC0A_1014
Loop Count (Channel Linking Disabled)
(DMA_TCD0_CITER_ELINKNO)
FC0A_1016 (DMA_TCD0_DOFF)
FC0A_1018 (DMA_TCD0_DLASTSGA)
(DMA_TCD0_BITER_ELINKYES)
FC0A_101C
(DMA_TCD0_BITER_ELINKNO)
FC0A_101E (DMA_TCD0_CSR)
TCD1 Source Address
FC0A_1020
(DMA_TCD1_SADDR)
TCD1 Transfer Attributes
FC0A_1024
(DMA_TCD1_ATTR)
TCD1 Signed Source Address Offset
FC0A_1026
(DMA_TCD1_SOFF)
388/2058
Table 164. DMA memory map(Continued)
Register name
DocID027809 Rev 4
Width
Access
(in bits)
8
R/W
8
R/W
8
R/W
32
R/W
16
R/W
16
R/W
32
R/W
32
R/W
32
R/W
32
R/W
32
R/W
16
R/W
16
R/W
16
R/W
32
R/W
16
R/W
16
R/W
16
R/W
32
R/W
16
R/W
16
R/W
RM0400
Reset value
Location
00h
on page 415
00h
on page 415
00h
on page 415
0000_000Xh
on page 416
000Xh
on page 417
000Xh
on page 418
0000_000Xh
on page 419
0000_000Xh
on page 419
0000_000Xh
on page 420
0000_000Xh
on page 421
0000_000Xh
on page 422
000Xh
on page 422
000Xh
on page 423
000Xh
on page 424
0000_000Xh
on page 425
000Xh
on page 425
000Xh
on page 426
000Xh
on page 427
0000_000Xh
on page 416
000Xh
on page 417
000Xh
on page 418
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