Software-Settable Interrupt Requests - STMicroelectronics SPC572L series Reference Manual

Interrupt Controller (INTC)
Reducing the number of priorities does cause some priority inversion, which reduces the
processor's ability to meet its deadlines. However, reducing the number of priorities can
reduce the size and latency through the interrupt controller. It also allows easier
management of ISRs with similar deadlines that share a resource. They can be placed at
the same priority without any further priority inversion, and they do not need to use the PCP
to access the shared resource.
18.7.7

Software-settable interrupt requests

The software-settable interrupt requests can be used in two ways. They can be used to
schedule a lower priority portion of an ISR and for processors to interrupt other processors
in a multiple processor system.
18.7.7.1 Scheduling a lower priority portion of an ISR
A portion of an ISR needs to be executed at the PRIn value in INTC_PSRn, which becomes
the PRI value in INTC_CPRn with the interrupt acknowledge. The ISR, however, can have a
portion of it which does not need to be executed at this higher priority. Therefore, executing
this later portion which does not need to be executed at this higher priority can prevent the
execution of ISRs which do not have a higher priority than the earlier portion of the ISR but
do have a higher priority than the later portion of the ISR needs. This preemptive scheduling
inefficiency reduces the processor's ability to meet its deadlines.
One option is for the ISR to complete the earlier higher priority portion, but then schedule
through the RTOS a task to execute the later lower priority portion. However, some RTOSs
can require a large amount of time for an ISR to schedule a task. Therefore, a second option
is for the ISR, after completing the higher priority portion, to set a SET bit in INTC_SSCIRn.
Writing a 1 to SET causes a software-settable interrupt request. This software-settable
interrupt request, which usually will have a lower PRIn value in the INTC_PSRn, therefore
will not cause preemptive scheduling inefficiencies.
18.7.7.2 Scheduling an ISR on another processor
Since the SET bits in the INTC_SSCIRn are memory mapped, processors in multiple
processor systems can schedule ISRs on the other processors. One possible application is
if one processor simply wants to command another processor to perform a piece of work,
and the initiating processor does not need to use the results of that work. If the initiating
processor needs to know if the processor executing the software-settable ISR has not
completed the work before asking it to again execute that ISR, it can check if the
corresponding CLR bit in INTC_SSCIRn is asserted before again writing a 1 to the SET bit.
Another application is the sharing of a block of data. For example, a first processor has
completed accessing a block of data and wants a second processor to then access it.
Furthermore, after the second processor has completed accessing the block of data, the
first processor again wants to access it. The accesses to the block of data must be done
coherently. The procedure is that the first processor writes a 1 to a SET bit on the second
processor. The second processor, after accessing the block of data, clears the
corresponding CLR bit and then writes 1 to a SET bit on the first processor, informing it that
it now can access the block of data.
18.7.8 Lowering priority within an ISR
In implementations without the software-settable interrupt requests in INTC_SSCIRn, one
way (besides scheduling a task through an RTOS) to prevent preemptive scheduling
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