Power Management; Overview; Power Management Framework - STMicroelectronics SPC572L series Reference Manual

Power management

9 Power management
9.1

Overview

SPC572Lx microcontrollers include a robust power management infrastructure for
applications to select various Operational and Low-power modes and monitor internal
voltages for High- and Low-voltage conditions. This monitoring is also used to ensure supply
voltages and internal voltages are within the required ranges before the microcontroller
leaves reset.
This chapter gives an overview of the built-in power management features.
The power management infrastructure encompasses the following modules:
•
Power Control Unit (MC_PCU): provides a status register, and the Power Management
Control Digital Interface (PMC_dig) submodule, which provides an interface to
configure and control internal voltages.
•
Clock Generation Module (MC_CGM): generates reference clocks for all the chip
blocks. It works in conjunction with internal clock gating logic to implement Low-power
modes.
•
Mode Entry Module (MC_ME): controls chip operational modes and mode transition
sequences. It also contains configuration, control and status registers accessible for
the application.
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See the respective module chapters for further details.
9.1.1

Power management framework

The power management framework supports a variety of configuration options. See
Figure 33
There are no separate functional power domains.
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System modes RESET, SAFE, TEST and DRUN are entered automatically on
system events or on application request.
User modes RUNx, HALT, and STOP control performance and consumption
during normal application operation. The modes are organized according to the
performance provided. Each mode is entered via a dedicated key-protected
register to avoid unwanted transition.
for more details. SPC572Lx implements a unique core voltage power domain.
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