Table 211. Pll Register Write Protection - STMicroelectronics SPC572L series Reference Manual

Clocking
Offset
00h
04h
08h
1. See Register Protection Configuration chapter for bit field details.
21.5.1.2 PLL register reset values
The reset values for the device-specific PLLDIG registers are shown in
Offset
(hex)
0008
21.5.1.3 Loss of clock detection
Loss of clock detection should be enabled at all times when the PLL is enabled. There is a
software option to generate a reset or interrupt in the event of a loss of clock condition. An
optional backup clock is implemented within the PLL that software may enable or disable.
21.5.1.4 PLLDIG initialization information
Configure PLL and related modules.
1. With PLL disabled, program PLL clock source in MC_CGM_AC3_SC[SELCTL]. Default
source is 16 MHz IRCOSC. Write MC_CGM_AC3_SC[SELCTL] = 1 to select XOSC as
source.
2. Program PLLDV[PREDIV], PLLDV[RFDPHI1], PLLDV[MFD] and PLLDV[RFDPHI].
3. If desired, modify the XOSC_CTL[EOCV] to adjust the external oscillator stabilization
count, used when the external oscillator is turned on (by the MC_ME).
4. If necessary, modify the CMU frequency meter values (CMU_MDR and CMU_FDR)
used to monitor the XOSC frequency. XOSC frequency is compared to the IRCOSC
source when XOSC is turned on.
Turn on XOSC and PLL.
5. Configure a mode configuration for turning on PLL and XOSC. In a mode configuration
register (for example, MC_ME_DRUN_MC) set MC_ME_<mode>_MC[XOSCON] = 1
and MC_ME_<mode>_MC[PLLON] = 1. If desired, also set
MC_ME_<mode>_MC[SYSCLK] = 2 for this new mode configuration to use PLL PHI
output) as the sysclk.
6. Enter that mode by two writes to MC_ME_CTRL register to enter that mode. This is
required even if entering the same mode.
Wait for the mode transition to complete.
7. Wait for the mode transition to complete by polling MC_ME_GS[S_MTRANS] or
enabling an interrupt for flag MC_ME_IS[I_MTC]. A timer, even if it is the watchdog,
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Table 211. PLL register write protection

PLL0 Control Register (PLL0CR)
PLL0 Status Register (PLL0SR)
PLL0 Divider Register (PLL0DIVR)
Table 212. PLL register reset values
PLL0DV — PLL0 Divider Register
DocID027809 Rev 4
Register
Register
RM0400
(1)
Protection
Yes
No
Yes
Table 212.
Reset value
(hex)
0000_0000