Table 461. Gtmdi_Ds Field Descriptions - STMicroelectronics SPC572L series Reference Manual

GTM Development Interface (GTMDI)
Register index: 6
31 30
R HLT 0
W
RESET: 0 0
15 14
R STP 0
W
RESET: 0 0
Table 461
Note: The HS1 and HS2 bit fields are cleared as soon as the GTM resumes normal operation
which is controlled by the CHR bit in the GTMDI_DC register. One exception is HS1[0] that
indicates system debug request, which is not cleared by CHR. This bit is cleared when
system debug request is negated.
Field
Halt Indication. The HLT bit indicates if the GTM IP is in Halt state, ready to receive debug
31 accesses.
HLT 0 GTM is running
1 GTM is in Halt state
Halt Status1. The HS1 field shows which source generated the halt condition. More than one
source can generate the halt condition at the same time. This register is only meaningful if the GTM
is halted. Its content indicates the halt sources that occurred immediately when the halt mode is
entered.
0000000000000No Trigger generated
1xxxxxxxxxxxxTIM
x1xxxxxxxxxxxTOM
xx1xxxxxxxxxxATOM
28–16
xxx1xxxxxxxxxSPEA
HS1 xxxx1xxxxxxxxSPEB
xxxxx1xxxxxxxARU
xxxxxx1xxxxxxDPLL
xxxxxxx1xxxxxMCSA
xxxxxxxx1xxxxMCSB
xxxxxxxxx1xxxTBU0 Watchpoint 1
xxxxxxxxxx1xxTBU1 Watchpoint 1
xxxxxxxxxxx1xTBU2 Watchpoint 1
xxxxxxxxxxxx1External through system debug enable signal
884/2058
29 28 27
0
0 0 0
13 12 11
0
0 0 0
Figure 408. GTMDI development status register (GTMDI_DS)
describes the GTMDI_DS register functions.

Table 461. GTMDI_DS field descriptions

DocID027809 Rev 4
26 25 24 23
HS1
0 0 0 0
10 9 8 7
HS2
0 0 0 0
Description
22 21 20 19
0 0 0 0
6 5 4 3
0 0 0 0
RM0400
18 17 16
0 0 0
2 1 0
0 0 0