Mode Transition Process - STMicroelectronics SPC572L series Reference Manual

RM0400
to HALT0
request), or
This mode is intended as a first-level low-power mode with
•
the core clocks frozen the additional core clocks frozen
•
only a few peripherals running
It is intended to be used by software to wait until it is required to do something and then to
react quickly (i.e., within a few system clock cycles of an interrupt event).
Note: It is good practice for software to ensure that the S_MTRANS bit in the ME_GS register has
been cleared on
has been fully restored before executing critical code.
56.4.2.7 STOP0
The chip enters this mode from one of the
field of the ME_MCTL register is written with "1010".
As soon as the above event has occurred, a
The mode configuration information for this mode is provided by the ME_STOP0_MC
register. This mode is fully configurable, and the ME_STOP0_MC register should be
programmed according to the system needs. The following clock sources are switched off in
this mode:
•
the primary PLL
•
the secondary PLL
The flash can be put in power-down mode as needed. If there is a
while any interrupt or wakeup event is active, the transition to
resultant mode being the current mode,
reset), and an invalid mode interrupt is not generated.
This can be used as an advanced low-power mode with the core clock frozen and almost all
peripherals stopped.
This mode is intended as an advanced low-power mode with
•
the core clock frozen
• the additional core clocks frozen
•
almost all peripherals stopped
It is intended to be used by software to wait until it is required to do something with no need
to react quickly (e.g., allow for system clock source to be re-started).
This mode can be used to stop all clock sources and thus preserve the chip status. When
exiting the
clock until the target clock is available.
Note: It is good practice for software to ensure that the S_MTRANS bit in the ME_GS register has
been cleared on
configuratoin has been fully restored before executing critical code.
56.4.3

Mode Transition Process

The process of mode transition follows the following steps in a pre-defined manner
depending on the current chip mode and the requested target mode. In many cases of
is aborted with the resultant mode being the current mode,
DRUN (on reset), and an invalid mode interrupt is not generated.
HALT0 mode exit to ensure that the previous
Mode
STOP0 mode, the 16 MHz internal RC oscillator clock is selected as the system
STOP0 mode exit to ensure that the previous
DocID027809 Rev 4
Mode Entry Module (MC_ME)
RUN0...3 modes when the TARGET_MODE bit
STOP0 mode transition request is generated.
SAFE (on SAFE mode request), or
SAFE (on SAFE
RUN0...3 mode configuratoin
STOP0 mode request
STOP0 is aborted with the
DRUN
RUN0...3 mode
1633/2058
mode
(on
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