Table 1015. Spu Register Summary - STMicroelectronics SPC572L series Reference Manual

RM0400
Table 1015
There are two instructions for the SPU registers:
•
Instruction to enable the SLU (first set of registers with offsets 1–0x49) registers is 4'h3
•
Instruction to enable the Counter Control Unit (second set of registers with offsets 1–
72) is 4'h2
Offset
(hex)
1 Level1 Mux Selection 0 (L1SEL0)
2 Level1 Mux Selection 1 (L1SEL1)
3 Level1 Mux Selection 2 (L1SEL2)
4 Level1 Mux Selection 3 (L1SEL3)
5 Level1 Mux Selection 4(L1SEL4)
6 Level1 Mux Selection 5 (L1SEL5)
7 Level1 Mux Selection 6 (L1SEL6)
8 Level1 Mux Selection 7 (L1SEL7)
9 Reserved for future use
A Reserved for future use
B Input Trigger Level Detection 2 (ITLD2)
C Input Trigger Level Detection 3 (ITLD3)
D Reserved
E Reserved
F CPU2 Processor Except Vector Prefix (C2PEVP)
10 Reserved for future use
11 Reserved for future use
12 Reserved
13 Reserved
14 CPU2 Interrupt Priority Selection (C2PIS)
15 Reserved for future use
16 Reserved for future use
17 Level2 Mux State0 Selection 0 (L20SEL0)
18 Level2 Mux State0 Selection 1 (L20SEL1)
19 Level2 Mux State0 Selection 2 (L20SEL2)
1A Level2 Mux State0 Selection 3 (L20SEL3)
1B Level2 Mux State1 Selection 0 (L21SEL0)
1C Level2 Mux State1 Selection 1 (L21SEL1)
1D Level2 Mux State1 Selection 2 (L21SEL2)
lists the memory mapped registers which control the operation of the SPU.

Table 1015. SPU register summary

Register
DocID027809 Rev 4
Sequence Processing Unit (SPU)
Reset
Access
Value
R/W 32'h0
R/W 32'h0
R/W 32'h0
R/W 32'h0
R/W 32'h0
R/W 32'h0
R/W 32'h0
R/W 32'h0
— —
— —
R/W 32'h0
R/W 32'h0
— —
— —
R/W 32'h0
— —
— —
— —
— —
R/W 32'h0
— —
— —
R/W 32'h0
R/W 32'h0
R/W 32'h0
R/W 32'h0
R/W 32'h0
R/W 32'h0
R/W 32'h0
Location
on page 1825
on page 1826
on page 1826
on page 1826
on page 1826
on page 1827
on page 1827
on page 1827
—
—
on page 1828
on page 1828
—
—
on page 1829
—
—
—
—
on page 1829
—
—
on page 1831
on page 1832
on page 1834
on page 1835
on page 1831
on page 1832
on page 1834
1821/2058
1863