Table 285. Pfcr3 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Flash memory controller (PFLASH Controller)
Name
0–1
P0_WCFG
15
BAF_DIS
28.4.1.3 Platform Flash Access Protection Register (PFAPR)
The PFlash Access Protection Register (PFAPR) is used to control read and write accesses
to the flash array.
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Table 285. PFCR3 field descriptions

Port0 Way Configuration. This field controls the configuration of the line buffers for a given
set across all four ways in the controller cache. The indexed set can be organized as a
"pool" of available resources, or with a fixed partition between instruction and data buffers.
In all cases, when a buffer miss occurs, the flash page is assigned a location within the
controller cache. Within the indexed set, the way is selected using a least-recently-used
replacement policy, and the entry is then marked as most-recently-used for that set. If the
flash access is for the next-sequential line (prefetch), the buffer is not marked as most-
recently-used until the given address produces a buffer hit.
This field is initialized by hardware reset.
00 All four buffers in an indexed set are available for any flash access, that is, there is no
partitioning of the buffers based on the access type.
01 Reserved
10 The buffers in an indexed set are partitioned into two groups with way 0 and 1 allocated
for instruction fetches and way 2 and 3 for data accesses.
11 Reserved
BAF Disable. This field controls executable access to the BAF (Boot Assist Flash) region of
the flash, where the access type is detected by evaluating {p0,p1}_hprot[0]. Once this field
is set, attempted instruction access attempts targeting the BAF region are aborted and
terminated with a system bus error.
The affect of this field applies to system bus transfers through both, Port0 and Port1.
Data-type accesses to the BAF region are not affected by this field.
Once this field is set, it becomes a read-only field and can only be cleared by hardware
reset. Once this field is set, any subsequent write attempts to modify this field are ignored
with an error-free data transfer termination.
This field is initialized by hardware reset.
0 Executable access to the BAF flash region is allowed.
1 Executable access to the BAF flash region is prohibited.
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