Table 516. Gtmint Module Memory Map - STMicroelectronics SPC572L series Reference Manual

GTM101 Integration (GTMINT) Module
Offset
0x00000 GTM-IP Version control register (GTM_REV)
0x00004 GTM-IP Global reset register (GTM_RST)
0x00008 GTM-IP Global control register (GTM_CTRL)
GTM-IP Timeout Address Register
0x0000C
(GTM_AEI_ADDR_XPT)
GTM-IP Interrupt Notification Register
0x00010
(GTM_IRQ_NOTIFY)
0x00014 GTM-IP Interrupt Enable (GTM_IRQ_EN)
GTM-IP Interrupt Force
0x00018
(GTM_IRQ_FORCINT)
0x0001C GTM-IP Interrupt Mode (GTM_IRQ_MODE)
0x00020 GTM-IP (GTM_EIRQ_EN)
0x00024 – 0x0002C
GTM-IP AEI Bridge Mode
0x00030
(GTM_BRIDGE_MODE)
GTM-IP AEI Bridge Pointer1
0x00034
(GTM_BRIDGE_PTR1)
GTM-IP AEI Bridge Pointer2
0x00038
(GTM_BRIDGE_PTR2)
0x0003C
GTM-IP TIM[m] auxiliary source selection
register (m = 0..1)
0x00040+m*0x04
(GTM_TIM[m]_AUX_IN_SRC)
0x00048 – 0x00058
0x0005C – 0x000BC
GTMMCR – GTM Module Configuration
0x000C0
Register
0x000C4
GTMINTCLR – GTM Interrupts Clear
0x000C8
Register
0x000CC GTMMAEICR – GTM AEI Control Register
0x000D0 – 0x000FC
0x00100 TBU global channel enable (TBU_CHEN)
966/2058

Table 516. GTMINT module memory map

Use
GTM-IP TOP-Level Configuration Registers
Top GTM Integration Registers
Time Base Unit (TBU) Configuration Registers
DocID027809 Rev 4
Access Reset value
0x101X_XXXX
R
2
R/W 0x0000_0000
R/W 0x0000_0001
R 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
Reserved
0x0400_0001
R/W
(3)
0x0040_0000
R
Cross Refs>3
R 0x0000_0000
Reserved
R/W 0x0000_0000
Reserved
Reserved
0xX000_X000
R/W
Cross Refs>3
Reserved
R/W 0x0000_0000
R/W 0x0000_0000
Reserved
R/W 0x0000_0000
RM0400
(1)
Location
See GTM
(2)
Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
<
2
See GTM Spec.
2
See GTM Spec.
2
See GTM Spec.
<
on page 984
on page 985
on page 986
2
See GTM Spec.