Table 428. Decfilter_Fintval Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Decimation Filter
37.3.2.9 Decimation Filter Final Integration Value register (DECFILTER_FINTVAL)
Address: DECFILTER_BASE + 0x0E0
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 368. Decimation Filter Final Integration Value register (DECFILTER_FINTVAL)
Field
Integration Sum Value
The SUM_VALUE[31:0] field holds the sum of filtered output values. The 17 most significant
bits hold the integer part, and the 15 least significant ones the fractional part of the integration
value. The control of the integration sum and update of this register is determined by the
register DECFILTER_MXCR (see <Cross Refs>Section 37.3.2.3, "Decimation Filter Module
Extended Configuration Register (DECFILTER_MXCR)"). The register is updated only upon
an integration output request.
SUM_VALUE should be taken as an unsigned number when the integrator is configured for
0-31
absolute operation (DECFILTER_MXCR bit SSIG=0), and a two's complement signed
SUM_VALUE[31:0]
number otherwise.
Note: If the DEFILTER_MXCR bit SSAT=1, the integration sum is saturated, so that if the
Note: If SSAT=0, DECFILTER_FINTVAL holds the integration sum modulo 2
824/2058
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0

Table 428. DECFILTER_FINTVAL field descriptions

accumulation overflows DECFILTER_FINTVAL holds the value 0xFFFFFFFF for
absolute integration (SSIG=0), or values 0x7FFFFFFF (positive saturation) and
0x80000000 (negative saturation) for signaled integration (SSIG=1).
the 15-bit fractional part).
DocID027809 Rev 4
6 7 8 9
SUM_VALUE[31:16]
0 0 0 0
22 23 24 25
SUM_VALUE[15:0]
0 0 0 0
Description
Access: User read only
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
17
RM0400
14 15
0 0
30 31
0 0
(considering