Bus Idle Diagnostic - STMicroelectronics SPC572L series Reference Manual

SENT Receiver (SRX)
channel being used, or it can be set at some fixed value determined by application, such as
1 µs. For example, if the high frequency receiver clock is 60 MHz, the required prescaler
value to generate a time stamp clock of 1 µs resolution is 60.
Note: The rollover of time stamp values should be determined in user software, by comparing the
time stamp values in previous and current messages that are read out. User software
should adjust the time stamp values in these messages accordingly, after reading them.
The time stamp for a Fast Message is sampled at the falling edge that comes at the end of
the calibration pulse (which is also the start of the status and communication nibble pulse)
and is stored in the message read buffer. However, if the current message is found to be in
error, the message buffer is discarded. Thus, the time stamp will be available to user
software for only those messages which do not have any error.
The time stamp for a serial message is sampled at the end of the message i.e. when the
serial message is completely received and when the message is found to have no errors.
the time stamp is stored in the message read buffer to be read by the user software. Again,
for messages with error the message and time stamp are discarded.
49.4.8.1 Limitation
Since the same counter is used for all channels, it may happen that more than 1 message is
received within the same time stamp across different channels. Hence the software would
not be able to determine the sequence of arrival of messages which have the same time
stamp value.
49.4.9

Bus Idle Diagnostic

This diagnostic checks the connected sensors for inactivity. SENT module can indicate if the
idle period on a particular channel has crossed the period defined by the programmed value
in Bus Idle Count (in
(CHn_CONFIG)). Status bit (bus_idle in
0 to (CH-1))
should write 1 to this clear this bit once it is read.
49.5 Clocks and resets
The SENT Receiver works on two clocks. First is the System Bus Clock that is used to
program the registers and read messages via DMA or Interrupt from the module's Register
Interface. Second is the High Frequency Receiver Clock or Protocol Clock that is used for
accurate message receiving operations. There is a single asynchronous reset which is the
system asynchronous reset and one internal reset for each of the channel logic.
49.5.1 Clocking strategy
Figure 804
1408/2058
Section 49.3.2.20: Channel 'n' Configuration Register (n = 0 to (CH-1))
(CHn_STATUS)) will be set when idle period crosses the allowed value. CPU
shows the clock domain in which each module is functioning.
DocID027809 Rev 4
Section 49.3.2.19: Channel 'n' Status Register (n =
RM0400