Figure 998. External Debug Resource Allocation Control (Edbrac0) Register - STMicroelectronics SPC572L series Reference Manual

RM0400
are allocated based on the settings of EDBRAC0 when EDBCR0
are ignored when EDBCR0
Hardware-owned resources that generate debug events update EDBSR0 instead of DBSR
and cause entry into debug mode if the event is not masked in EDBSRMSK0, while
software-owned resources that generate debug events if DBCR0
causing debug interrupts to occur if MSR
hardware, and is read-only to software.
The DBSR status register is always owned by software. Debug status bits in DBSR are set
by software-owned debug events only while Internal Debug mode is enabled. When debug
interrupts are enabled (MSR
DBCR0
IDM
set bit in DBSR by an event that is software-owned (other than MRR, DAC_OFST, or VLES)
will cause a debug interrupt to be generated.
Debug status bits in EDBSR0 are set by hardware-owned debug events only while External
Debug mode is enabled (EDBCR0
an event that is hardware-owned (other than IDE, DAC_OFST, or VLES) will cause entry
into debug mode unless entry is masked via EDBSRMSK0.
If EDBCR0
masked from being set by hardware.
Software-owned resources may be modified by software, but only the corresponding control
bits in DBCR0–8 are affected by execution of a mtspr, thus only a portion of these registers
may be affected, depending on the allocation settings in EDBRAC0. The debug interrupt
handler is still responsible for clearing DBSR bits for software-owned resources prior to
returning to normal execution. Hardware always has full access to all registers and register
fields through the OnCE register access mechanism, and it is up to the debug firmware to
properly implement modifications to these registers with read-modify-write operations to
implement any control sharing with software. Settings in EDBRAC0 should be considered
by the debug firmware in order to preserve software settings of control and status registers
as appropriate when hardware modifications to the debug registers is performed.
The EDBRAC0 register is shown in

Figure 998. External Debug Resource Allocation Control (EDBRAC0) register

0
0 1 2 3 4 5 6
SPR - 638; Read-only by Software; Reset - Unaffected by p_reset_b, reset to 0x00000180 by m_por or while in the
Table 947
that EDBRAC0 controls are disabled when EDBCR0EDM=0.
=0.
EDM
=1 DBCR0
DE
=1 and EDBCR0 =1 and software is allocated resource(s) via EDBRAC0), a
EDM
=1, DBSR status bits corresponding to hardware-owned debug events are
EDM
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
test-logic-reset OnCE controller state
provides bit definitions for the Debug External Resource Control Register. Note
DocID027809 Rev 4
e200z215An3 Core Debug Support
=1. EDBRAC0 is controlled via the OnCE port
DE
=1 and EDBCR0
IDM
=1). When EDBCR0
EDM
Figure 998.
0
=1. EDBRAC0 settings
EDM
=1 update DBSR,
IDM
=0, or MSR =1,
EDM DE
=1, a set bit in EDBSR0 by
EDM
0 0
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