Table 1105. Data Trace Exception Summary - STMicroelectronics SPC572L series Reference Manual

e200z215An3 Nexus 3 Module
Note: For Core (e200z215An3)-based CPUs, the doubleword encoding (p_tsiz = 0b000) may also
indicate a doubleword access and will be sent out as a single Data Trace Message with a
single 64-bit data value.
Note: The debug/development tool will need to distinguish the two cases based on the family of
processor.
66.13.2.3 Data Trace Synchronization messages
A Data Trace Write/Read with Sync. message is messaged via the auxiliary port (provided
Data Trace is enabled) for the following conditions (see
•
Initial Data Trace Message after exit from system reset or whenever Data Trace is
enabled.
•
Upon returning from a CPU Low Power state.
•
Upon returning from Debug Mode.
•
After occurrence of queue overrun (can be caused by any trace message), provided
Data Trace is enabled.
•
After the periodic data trace counter has expired indicating 255 without-sync Data
Trace messages have occurred since the last with-sync message occurred.
•
Upon assertion of the Event In (nex_evti_b) pin, the first Data Trace Message will be a
synchronization message if the EIC bits of the DC1 Register have enabled this feature.
•
Upon Data Trace Write/Read after the previous DTM message was lost due to an
attempted access to a secure memory location (for SOC's w/ security).
•
Upon Data Trace Write/Read after the previous DTM message was lost due to a
collision entering the FIFO between the DTM message and any two of the following:
Watchpoint message, Ownership Trace message, or Program Trace message.
Data Trace Synchronization Messages provide the full address (without leading zeros) and
insure that development tools fully synchronize with Data Trace regularly. Synchronization
messages provide a reference address for subsequent DTMs, in which only the unique
portion of the Data Trace address is transmitted. The format for Data Trace Write/Read with
Sync. Messages is as follows:
(1–64 bits)
Data Value
Max length = 111 bits; Min length = 17 bits
Exception conditions that result in Data Trace Synchronization are summarized in
Table 1105.
Exception Condition
System Reset Negation
Data Trace Enabled
1962/2058
Figure 1177. Data Write/Read with Sync message format
(4 bits)
(1–32 bits)
Full Address Data Size

Table 1105. Data Trace Exception summary

At the negation of JTAG reset (j_trst_b), queue pointers, counters, state machines,
and registers within the Nexus 3 module are reset. If Data Trace is enabled, the first
Data Trace Message is a Data Write/Read w/ Sync. Message.
The first Data Trace Message (after Data Trace has been enabled) is a
synchronization message.
DocID027809 Rev 4
Table 1105):
(1 bit) (4 bits)
Source
(0) TCODE (001101 or 001110)
Proc.
Exception Handling
RM0400
(6 bits)