Functional Description - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
Contains data to be captured in JIN_IPS register upon exit of Update-DR state when
JIN Data
executing WRITE_JIN JTAG instruction.
61.4

Functional description

The JDC module provides the ability to shift in data via the JTAG port and capture that data
into a memory mapped register that can be accessed via IPS. It also provides the ability to
capture data written to a memory mapped register into a JTAG shift register for output via
the JTAG port. An overview of the module functionality is described below.
•
A software write to the JDC_JOUT_IPS register sets the JOUT_RDY flag bit, indicating
new data is available to be read from the JOUT register via the JTAG port. The state of
the JOUT_RDY bit is reflected in the JDC_MSR and also ported out to the JOUT
register. A JTAG read of the JOUT register via execution of the JOUT_READ
instruction with a JOUT_RDY bit whose value is logic 1 indicates the register contains
new data. The JOUT_RDY flag bit is cleared upon exit of the Capture-DR JTAG state
during execution of the JOUT_READ instruction. Clearing the JOUT_RDY bit indicates
to software that a new data value can be written to the JDC_JOUT_IPS register.
•
A JTAG write to the JIN register via execution of the JIN_READ JTAG instruction
updates the contents of the JDC_JIN_IPS register upon exit of the Update-DR state.
An update of the JDC_JIN_IPS register sets the JIN_RDY flag bit, indicating new data
is available to be read via IPS. The state of the JIN_RDY bit is reflected in the
JDC_MSR register and also ported out to the JOUT register. The JIN_RDY flag bit is
cleared upon software read of the JDC_JIN_IPS register. A JTAG read of the JOUT
register with a JIN_RDY value of logic 0 indicates new data can be written to the JIN
register.
61.4.1 IPS register access
IPS access is available to the registers described in <Cross Refs>Section 61.3.1, Register
descriptions.
61.4.2 JTAG register access
Refer to the JTAGC documentation for information on how to access the JTAG registers.
61.4.2.1 JDC block instructions
The JDC block implements the IEEE 1149.1-2001 defined instructions listed in
This section gives an overview of each instruction; refer to the IEEE 1149.1-2001 standard
for more details. All undefined opcodes are reserved.
Instruction
Reserved
JOUT_READ
Table 1004. JIN JTAG register field descriptions
Table 1005. JTAG instructions
Code[4:0]
00001 Factory debug reserved
Selects JOUT data register. Data from JDC_JOUT_IPS is captured into
00010 JOUT data register upon entry to Capture-DR state while JOUT_READ is
active.
DocID027809 Rev 4
JTAG Data Communication (JDC)
Description
Instruction Summary
Table 1005.
1801/2058
1802